XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 362

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Conversely, if the user configures the Receive STS-3 TOH Processor block to “tally” B2 errors on a “per-
frame” basis, then it will declare a single B2 byte error, anytime at least one bit, within the 3 or 12 B2 bytes
(within a given incoming STS-3 frame) is determined to be in error. In this case, the Receive STS-3 TOH
Processor block will at most declare one B2 byte error, per STS-3 frame.
The user can configure the Receive STS-3 TOH Processor block to “tally” B2 errors on a “per-bit” basis, by
setting Bit 1 (B2 Byte Error Type), within the “Receive STS-3 Transport Control Register – Byte 0” to “0”, as
depicted below.
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
Likewise, the user can configure the Receive STS-3 TOH Processor block to “tally” B2 Byte errors on a “per-
frame” basis, by setting Bit 1 (B2 Byte Error Type) to “1”, as depicted below.
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
This configuration option, on how the Receive STS-3 TOH Processor block “tallies” B2 byte errors impacts the
following functions.
• The SD Defect Declaration and Clearance Criteria
• The SF Defect Declaration and Clearance Criteria
•
Transport – B2 Byte Error Count” Registers.
2.3.1.13.2
The XRT94L33 permits the user to specify three parameters to define the SD Defect Declaration criteria.
• The minimum number of B2 byte errors (e.g., a B2 byte error-threshold) accumulated over a given “SD Set
Interval” time period. From this point on, this particular “B2 Byte Error” threshold will be referred to as the “SD
Defect Declare B2 Byte Error” Threshold.
• The length (in terms of STS-3 frame periods) of this “SD Set Interval” monitoring time period for the SD
Detector to tally B2 byte errors. From this point on, this particular “user-defined” monitoring time period will be
referred to as the “SD Defect Declare Monitor” time.
• The maximum number of B2 byte errors that will be counted within a sub-internal period towards the
declaration of the SD Defect condition. From this point on, this maximum number of B2 byte errors will be
referred to as the “SD Detect B2 Error Burst Limit”.
Once the user defines these parameters, then the Receive STS-3 TOH Processor block will begin to count
the cumulative number of B2 errors that it detects within a “sliding window” of time. The length of this “sliding
window of time” is dictated by the “SD Defect Declare Monitor” time period.
Unused
Unused
B
B
The amount by which the Receive STS-3 TOH Processor block will increment the “Receive STS-3
R/O
R/O
IT
IT
0
0
7
7
The SD (Signal Degrade) Defect Declaration Criteria
SF Defect
SF Defect
Enable
Enable
Detect
Detect
B
B
R/W
R/W
IT
IT
0
0
6
6
SD Defect
SD Defect
Enable
Enable
Detect
Detect
B
B
R/W
R/W
IT
IT
0
0
5
5
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Descramble
Descramble
Disable
Disable
B
B
R/W
R/W
IT
IT
0
0
4
4
362
SDH/SONET*
SDH/SONET*
B
B
R/W
R/W
IT
IT
0
0
3
3
REI-L Error
REI-L Error
Type
Type
B
B
R/W
R/W
IT
IT
0
0
2
2
Error Type
Error Type
B2 Byte
B2 Byte
B
B
R/W
R/W
IT
IT
0
1
xr
1
1
Error Type
Error Type
B1 Byte
B1 Byte
B
B
R/W
R/W
IT
IT
0
0
0
0