XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 131

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Figure 5 Behavior of the Microprocessor Interface Signals, during an “Intel-type” Programmed I/O
Write Operation
1.3.4
If the XRT94L33 is interfaced to a “Motorola-type” µC/µP (e.g., the MC680X0 family, etc.); it should be
configured to operate in the “Motorola” mode. Motorola-type Programmed I/O “Read” and “Write” operations
are described below.
1.3.4.1
Whenever a “Motorola-type” µC/µP wishes to read the contents of a register or some location within the
Receive J0 or J1 Message Buffer, within the XRT94L33 it should do the following.
1. Assert the ALE_AS (Address-Strobe) input pin by toggling it low. This step enables the Address Bus input
2. Place the address of the “target” register (or buffer location) within the XRT94L33, on the Address Bus
3. At the same time, the Address Decoding circuitry (within the user’s system) should assert the CS* (Chip
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate “Address Setup” time),
5. Further, the µC/µP should indicate that this cycle is a “Read” cycle by setting the WRB_RW (R/W*) input
6. Next the µC/µP should initiate the current bus cycle by toggling the RdB_DS (Data Strobe) input pin “low”.
After some settling time, the data on the “bi-directional” data bus will stabilize and can be read by the µC/µP.
After the µC/µP detects the Rdy_Dtck signal (from the XRT94L33 UNI) it will terminate the Read Cycle by
Figure 6 presents a timing diagram which illustrates the behavior of the Microprocessor Interface signals
during a “Motorola-type” Programmed I/O Read Operation.
ALE_AS
RdB_DS
WRB_RW
D[7:0]
A[14:0]
CS*
drivers, within the Microprocessor Interface Block of the XRT94L33 IC.
input pins, A[14:0].
Select) input pin of the XRT94L33, by toggling it “low”. This action enables further communication
between the µC/µP and the XRT94L33 Microprocessor Interface block.
the µC/µP should toggle the ALE_AS input pin “high”. This step causes the XRT94L33 to latch the
contents of the “Address Bus” into its internal circuitry. At this point, the address of the register or buffer
location within the XRT94L33 has now been selected.
pin “high”.
This step enables the bi-directional data bus output drivers, within the XRT94L33 UNI device. At this
point, the bi-directional data bus output drivers will proceed to driver the contents of the “Address” register
onto the bi-directional data bus, D[7:0].
The XRT94L33 UNI will indicate that this data can be read by asserting the Rdy_Dtck (DTACK) signal.
toggling the “RdB_DS” (Data Strobe) input pin “high”.
P
ROGRAMMED
T
HE
M
OTOROLA
I/O A
M
ODE
CCESS IN THE
R
EAD
Address of Target Register
C
YCLE
M
Data to be Written
OTOROLA
131
M
ODE
XRT94L33
Rev.1.2.0.