XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 49

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
AD14
TXSENDMSG_2:
STS1TXA_PL_2
I
TTL
STS-1 Transmit Telecom Bus – Payload Indicator Signal
input/Transmit HDLC Controller block Send Message
Command Input pin – Channel 2:
The exact function of this input pin depends upon whether the
STS-1 Telecom Bus Interface for Channel 2 has been enabled
or not.
If STS-1 Telecom Bus (Channel 2) has been enabled –
STS-1 Transmit Telecom Bus – Payload Indicator Signal –
Channel 2:
This input pin indicates whether or not “Transport Overhead”
(TOH) bytes are being input via the “TXA_D_2[7:0]” input pins.
This input pin should be pulled “low” for the duration that the
STS-1 Transmit Telecom Bus is receiving a TOH byte, via the
“TXA_D_2[7:0]” input pins. Conversely, this input pin should
be pulled “high” at all other times.
Note:
If STS-1 Telecom Bus (Channel 2) has NOT been enabled:
If STS-1 Telecom Bus (Channel 2) has not been enabled, then
this particular pin can either be configured to function as the
“TxSENDMSG_2” input pin (if the DS3/E3 Framer block within
Channel 2 has been configured to operate in the “High-Speed
HDLC Controller Mode), or the user should simply tie this input
pin to GND.
“TxSENDMSG_2” input pin is described below.
TXSENDMSG_2 (Transmit HDLC Controller block Send
Message Command Input – High Speed HDLC Controller
Mode ONLY)
This input pin permits the user to command the Transmit
HDLC Controller block (associated with Channel 2) to begin
sampling and latching the data which is being applied to the
“TxHDLCDat_2[7:0]” input pins.
If the user pulls this input pin “high”, then the Transmit HDLC
Controller block samples and latches the data which is applied
to the “TxHDLCDat_2[7:0]” input pins upon the rising edge of
“TxHDLCClk_2”. Each byte of this sampled data will ultimately
be encapsulated into an outbound HDLC frame and will be
mapped into the payload bits within the outbound DS3/E3
frames via the DS3/E3 Frame Generator block.
If the user pulls this input pin “low” then the Transmit HDLC
Controller block will NOT sample and latch the contents on the
“TxHDLCDat_2[7:0]” input pins, and the Transmit HDLC
Controller block will simply generate a continuous stream of
flag sequence octets (0x7E).
Note:
49
The user should tie this pin to GND if the DS3/E3
“STS1TXA_CK_2”.
Framer block has NOT been configured to operate
in the “High-Speed HDLC Controller” Mode.
This input signal is sampled upon the falling edge of
The details of this pin’s role as the
XRT94L33
Rev.1.2.0.