XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 140

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Each of the “Operation Block Interrupt Status” Registers presents the “interrupt-request” status of each
functional block, within the chip. The purpose of these two registers is to help the µC/µP identify which
functional block(s) has requested the interrupt. Whichever bit(s) are asserted, in this register, identifies which
block(s) have experienced an “interrupt-generating” condition as presented in Table _. Once the µC/µP has
read this register, it can determine which “branch” within the interrupt service routine that it must follow in
order to properly service this interrupt.
The XRT94L33 ATM UNI/PPP IC further supports the Operational Block hierarchy by providing the Operation
Block Interrupt Enable Register – Bytes 1 and 0. The bit format of these two registers are identical to that for
the Operation Block Interrupt Status Registers – Bytes 1 and 0, and are presented below for the sake of
completeness.
Operation Block Interrupt Enable Register – Byte 1 (Address Location = 0x0116)
Operation Block Interrupt Enable Register – Byte 0 (Address Location = 0x0117)
These Operation Block Interrupt Enable registers permit the user to individually enable or disable the interrupt
requesting capability of the functional blocks within the XRT94L33. If a particular bit-field, within this register
contains the value “0”, then the corresponding functional block has been disabled for generating any interrupt
requests. Conversely, if that bit-field contains the value “1”; then the corresponding functional block has been
enabled for interrupt generation (e.g., those potential interrupts, within the “enabled functional block” that are
enabled at the source level are now enabled). The user should be aware of the fact that each functional
block, within the XRT94L33 contains multiple potential interrupt sources. Each of these lower level interrupt
sources contain their own set of interrupt enable bits and interrupt status bits, existing in various on-chip
registers.
Op Control
Processor
ATM Cell
Interrupt
Interrupt
Receive
Enable
Enable
Block
Block
B
B
R/W
R/W
IT
IT
0
0
7
7
STS-3 TOH
Processor
Interrupt
Interrupt
Receive
DS3/E3
Mapper
Enable
Enable
Block
Block
B
B
R/W
R/W
IT
IT
0
0
6
6
Processor
SONET/
Interrupt
Receive
Unused
STS-3c
Enable
Block
B
B
POH
R/W
R/W
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
STS-1 TOH
Processor
Processor
Interrupt
Interrupt
Receive
Receive
Enable
Enable
Block
Block
B
B
R/W
PPP
R/W
IT
IT
0
0
4
4
140
STS-1 POH
Processor
Processor
ATM Cell
Transmit
Receive
Interrupt
Interrupt
Enable
Enable
Block
Block
B
B
R/W
R/W
IT
IT
0
0
3
3
Interrupt
DS3/E3
Framer
Enable
Block
B
B
R/W
R/O
IT
IT
0
0
2
2
Unused
Interface
Interrupt
Receive
Enable
Block
B
B
Line
R/W
R/O
IT
IT
0
0
1
1
xr
Processor
Transmit
Interrupt
Unused
Enable
Block
B
B
PPP
R/W
R/O
IT
IT
0
0
0
0