XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 232

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
This step configures the “Transmit STS-3c POH Processor” block to read out the contents of the “Transmit
Path – Transmit J1 Byte Value” register; and load this value into the “J1 byte-field” within each outbound STS-
3c SPE.
STEP 2 – Write the desired byte value (for the “outbound” J1 byte) into the “Transmit STS-3c Path –
Transmit J1 Byte Value” register.
The bit-format of this register is presented below.
Transmit STS-3c Path – Transmitter J1 Value Register (Address = 0x1993)
2.2.7.3.4.4
The Transmit STS-3c POH Processor block permits the user to source the contents of the J1 byte via the
“TxPOH_n” input port. The user can configure the Transmit STS-3c POH Processor block to support this
feature by performing the following steps.
STEP 1 – Write the value “[1, 1]” into Bits 1 and 0 (J1 Type[1:0]) within the “Transmit STS-3c Path –
Transmit J1 Control” Register; as depicted below.
Transmit STS-3c Path – Transmit J1 Control” Register (Address = 0x19BB)
This step configures the “Transmit STS-3c POH Processor” block to accept the value of the J1 byte, via the
“TxPOH_n” input port and load this value into the J1 byte position within each outbound STS-3c SPE.
STEP 2 – Begin providing the values of the “outbound” J1 byte message to the “TxPOH_n” input port.
The procedure for applying the J1 byte to the “TxPOH_n” input port is presented below.
Using the “TxPOH” Input Port to insert the J1 byte value into the outbound STS-3c SPE data-stream
If the user intends to externally insert the J1 byte into the outbound STS-3c SPE, via the “TxPOH_n” input
port, then they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD
solution) to do to the following.
• Continuously sample the “TxPOHEnable_n” and the “TxPOHFrame_n” output pins upon the rising edge of
the “TxPOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxPOH Input Port” is presented below in
B
B
R/W
R/O
IT
IT
X
0
7
7
Setting and Controlling the “Outbound” J1 Byte via External Input pin
B
B
R/W
R/O
IT
IT
X
0
6
6
Unused
B
B
R/W
R/O
IT
X
IT
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Transmit_J1_Byte[7:0]
B
B
R/W
R/O
IT
IT
X
0
4
4
232
J1 Message Length[1:0]
B
B
R/W
R/W
IT
X
IT
0
3
3
B
B
R/W
R/W
IT
IT
X
0
2
2
B
B
R/W
R/W
IT
X
IT
1
1
1
xr
J1 Type[1:0]
B
B
R/W
R/W
IT
IT
X
1
0
0