XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 17

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
G4
K5
TxAPSReq
TxA_PL/
TxSBFP
I/O
O
I
CMOS
CMOS
TTL/
TTL
Transmit STS-3/STM-1 Frame Alignment Sync Input:
The Transmit STS-3 TOH Processor Block can be configured to
initiate its generation of a new “outbound” STS-3/STM-1 frame
based upon an externally supplied 8kHz clock signal to this input
pin. If the user opts to use this feature, then the Transmit STS-
3/STM-1 Telecom Bus Interface will begin transmitting the very
first byte of given STS-3 or STM-1 frame, upon sensing a rising
edge (of the 8kHz signal) at this input pin.
Notes:
1.
2.
3.
4.
Transmit STS-3/STM-1 Telecom Bus Interface – Payload
Data Indicator Output Signal:
This output pin indicates whether the Transmit STS-3/STM-1
Telecom Bus Interface is currently placing a Transport Overhead
byte or a “non-Transport Overhead Byte (e.g., STS-1 SPE, STS-
3c SPE, VC-3 or VC-4 data) via the “TXA_D[7:0]” output pins.
This output pin is pulled “low” for the duration that the Transmit
STS-3/STM-1 Telecom Bus Interface is transmitting a Transport
Overhead byte via the “TXA_D[7:0]” output pins.
Conversely, this output pin is pulled “high” for the duration that
the STS-3/STM-1 Transmit Telecom Bus is transmitting
something other than a Transport Overhead byte via the
“TXA_D[7:0]” output pins.
Transmit Payload APS Bus Interface – Request Input/Output
pin:
This pin can only be configured to operate in this role if the
XRT94L33 has been configured to operate in either the “ATM
UNI” or “PPP over STS-3c” Mode.
17
If the user connects this input pin to GND, then the Transmit
STS-3 TOH Processor block will generate its “outbound”
STS-3/STM-1 frames asynchronously, with respect to any
input signal.
This input signal must be synchronized with the signal that is
supplied to the REFTTL input pin. Failure to insure this will
result in bit errors being generated within the outbound STS-
3/STM-1 signal.
The user must supply an 8kHz pulse (to this input pin) that
has a width of approximately 51.4412.8ns (one 19.44MHz
clock period). The user must not apply a 50% duty cycle
8kHz signal to this input pin.
Register “HRSYNC_DLY” (Address Location: 0x0135)
defines the timing for TxSBFP input pin.
XRT94L33
Rev.1.2.0.