XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 430

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Note:
STEP 2 – Check and Verify that there is sufficient space available (within the Receive Cell Insertion
Buffer) to handle this cell.
This can be accomplished by one of two approaches.
• Polling approach
• Interrupt-driven approach.
Each of these approaches is described below.
Executing STEP 2 using the Polling Approach
The user can determine whether or not there is room (to write another ATM cell of data) in to the “Receive
Cell Insertion” Buffer” by polling the state of Bit 1 (Insertion Memory ROOM) within the “Receive ATM Cell –
Memory Control Register” as depicted below.
Receive ATM Cell – Memory Control Register (Address = 0xN713)
If Bit 1 (Insertion Memory ROOM) is set to “1” then the “Receive Cell Insertion Buffer” is NOT too full to accept
another cell. At this point, the Microprocessor can now move onto STEP 3.
Conversely, if Bit 1 is set to “0” then the “Receive Cell Insertion Buffer” is too full to accept another cell. The
Microprocessor Interface should continue to poll the state of this bit-field and wait until this bit-field toggles to
“1”.
Executing STEP 2 using the Interrupt-Driven Approach
In order to reduce or eliminate the Microprocessor Overhead of continuously polling the state of Bit 1, the user
can use the “Receive Cell Insertion” Interrupt feature, within the chip. If the Microprocessor invokes this
feature, then the XRT94L33 will generate an interrupt anytime a cell (residing in the Receive Cell Insertion
Buffer) has been inserted into the “Receive Input Data Path” (thereby freeing up some space within the
Receive Cell Insertion Buffer).
The user can enable the “Receive Cell Insertion” Interrupt by setting Bit 4 (Cell Insertion Interrupt Enable),
within the “Receive ATM Cell Processor – Interrupt Enable” Register to “1” as indicated below.
B
B
R/O
R/O
IT
IT
0
0
7
7
This step should typically be performed upon power-up, prior to writing in any ATM cell data into the “Receive
Cell Insertion Buffer”. This step is not necessary after the first cell has been written into the “Receive Cell
Insertion Buffer” following a power cycle to the chip.
Unused
Unused
B
B
R/O
R/O
IT
IT
0
0
6
6
B
B
R/O
R/O
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Extraction
Extraction
RESET*
RESET*
Memory
Memory
B
B
R/W
R/W
IT
IT
1
1
4
4
430
Extraction
Extraction
Memory
Memory
CLAV
CLAV
B
B
R/W
R/W
IT
IT
0
0
3
3
Insertion
Insertion
RESET*
RESET*
Memory
Memory
B
B
R/W
0->1
R/W
IT
IT
1
2
2
Insertion
Insertion
Memory
Memory
ROOM
ROOM
B
B
R/W
R/W
IT
IT
X
1
1
1
xr
Write SoC
Write SoC
Insertion
Insertion
Memory
Memory
B
B
R/W
R/W
IT
IT
0
0
0
0