XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 378
XRT94L33IB-L
Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Specifications of XRT94L33IB-L
Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
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XRT94L33
Rev.1.2.0.
Additionally, now suppose that the user writes in the value “0x000100” into the “Receive STS-3 Transport –
Receive SF Clear Monitor Interval” Registers; as depicted below.
Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2 (Address = 0x115D)
Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1 (Address = 0x115E)
Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 0 (Address = 0x115F)
Once the user has executed these two steps, then the “SF Clearance Criteria” will be as summarized below.
• B2 Error Threshold = 0x08 (or 8) B2 Errors
• SF Clear Interval = 0x100 (or 256 SONET frame periods)
Hence, the Receive STS-3 TOH Processor block will accumulate B2 errors over 2048 (e.g. 8 * 256) SONET
frame periods.
At this point, the Receive STS-3 TOH Processor block will proceed to count B2 errors. If the Receive STS-3
TOH Processor block is currently declaring the SF condition; it will now clear the SF condition if it detects less
than 8 B2 errors, within a 256ms period (e.g., 2048 SONET frame periods); then it will clear the SF condition.
Occurrences whenever the Receive STS-3 TOH Processor block clears the SF Condition
Anytime the Receive STS-3 TOH Processor block clears the SF Condition, then it will do the following.
It will generate the “Change of SF Condition” Interrupt
Note:
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
7
7
7
The Receive STS-3 TOH Processor block will indicate that it is generating this interrupt by toggling the “INT*”
output pin “low” and be setting the “Change of SF Condition Interrupt Status” bit to “1”, as depicted below.
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
6
6
6
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
5
SF_CLEAR_MONITOR_WINDOW[23:16]
SF_CLEAR_MONITOR_WINDOW[15:8]
SF_CLEAR_MONITOR_WINDOW[7:0]
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
4
4
4
378
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
3
3
3
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
2
2
2
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
1
1
1
xr
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
1
0
0
0
0
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