AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 12

• Manufacturer Part Number: AGLN030V2-ZVQG100
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN030V2-ZVQG100

• Processor Series: AGLN030
• Core: IP Core
• Number Of Macrocells: 256
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 77
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 30 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO nano Device Overview
Figure 1-5 • IGLOO nano Flash*Freeze Mode
Figure 1-6 • VersaTile Configurations
1- 6
X1
X2
X3
LUT-3 Equivalent
LUT-3
Flash*Freeze Technology
The IGLOO nano device has an ultra-low power static mode, called Flash*Freeze mode, which retains all
SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology
enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os, and clocks
can still be driven and can be toggling without impact on power consumption, and the device retains all
core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their
previous state or be tristated during Flash*Freeze mode.
Alternatively, I/Os can be set to a specific state using weak pull-up or pull-down I/O attribute
configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device
consumes as little as 2 µW in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. Refer to
Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode
usage is not planned.
VersaTiles
The IGLOO nano core consists of VersaTiles, which have been enhanced beyond the ProASIC
core tiles. The IGLOO nano VersaTile supports the following:
Refer to
•
•
•
•
Y
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Figure 1-6
for VersaTile configurations.
D-Flip-Flop with Clear or Set
Data
Flash*Freeze
Mode Control
CLK
CLR
D-FF
R ev isio n 1 1
Flash*Freeze Pin
Actel IGLOO nano
Y
FPGA
Figure 1-5
Enable D-Flip-Flop with Clear or Set
Enable
Data
for an illustration of entering/exiting
CLK
CLR
D-FF
Y
PLUS®