AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 23

FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano

AGLN030V2-ZVQG100

Manufacturer Part Number
AGLN030V2-ZVQG100
Description
FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
Manufacturer
Actel
Datasheet

Specifications of AGLN030V2-ZVQG100

Processor Series
AGLN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
77
Supply Voltage (max)
1.5 V
Supply Current
6 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
30 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGLN030V2-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGLN030V2-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger
3.3 V LVCMOS Wide Range
3.3 V LVCMOS Wide Range – Schmitt Trigger
2.5 V LVCMOS
2.5 V LVCMOS – Schmitt Trigger
1.8 V LVCMOS
1.8 V LVCMOS – Schmitt Trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt Trigger
1.2 V LVCMOS
1.2 V LVCMOS – Schmitt Trigger
1.2 V LVCMOS Wide Range
1,2 V LVCMOS Wide Range – Schmitt Trigger
Notes:
1. P
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. Applicable to IGLOO nano V2 devices operating at VCCI ≥ VCC.
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. P
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
4. Applicable for IGLOO nano V2 devices operating at VCCI ≥ VCC.
AC9
AC10
is the total dynamic power measured on V
is the total dynamic power measured on V
Power per I/O Pin
Applicable to IGLOO nano I/O Banks
Applicable to IGLOO nano I/O Banks
3
4
2
3
3
3
3
CCI
CCI
C
.
LOAD
.
5
5
5
5
5
5
R ev i si o n 1 1
(pF)
VCCI (V)
3.3
3.3
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.2
1.2
1.2
VCCI (V)
3.3
3.3
2.5
1.8
1.5
1.2
IGLOO nano Low Power Flash FPGAs
P
Dynamic Power
AC9
P
Dynamic Power
AC10
1
(µW/MHz)
16.38
18.89
16.38
18.89
4.71
6.13
1.64
1.79
0.97
0.96
0.57
0.52
0.57
0.52
107.98
107.98
61.24
31.28
21.50
15.22
(µW/MHz)
1
2
2 -9

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