AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 46

FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano

AGLN030V2-ZVQG100

Manufacturer Part Number
AGLN030V2-ZVQG100
Description
FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
Manufacturer
Actel
Datasheet

Specifications of AGLN030V2-ZVQG100

Processor Series
AGLN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
77
Supply Voltage (max)
1.5 V
Supply Current
6 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
30 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGLN030V2-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGLN030V2-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
IGLOO nano DC and Switching Characteristics
Table 2-45 • Minimum and Maximum DC Input and Output Levels
Figure 2-8 • AC Loading
Table 2-46 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
2- 32
2.5 V
LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input LOW (V)
0
*
Measuring point = Vtrip. See
current is larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general
purpose 2.5 V applications.
–0.3
–0.3
–0.3
–0.3
Test Point
Datapath
VIL
0.7
0.7
0.7
0.7
Table 2-23 on page 2-20
1.7
1.7
1.7
1.7
5 pF
Input HIGH (V)
VIH
3.6
3.6
3.6
3.6
2.5
Enable Path
Test Point
VOL
0.7
0.7
0.7
0.7
R = 1 k
for a complete table of trip points.
R ev i sio n 1 1
VOH
1.7
1.7
1.7
1.7
Measuring Point* (V)
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
I
OL
2
6
4
8
1.2
I
OH
2
6
8
4
HZ
ZH
/ t
/ t
LZ
I
LZ
HZ
OSL
16
16
32
32
ZHS
/ t
/ t
ZL
/ t
ZH
3
/ t
ZL
/ t
Max., mA
ZLS
/ t
ZHS
ZLS
I
C
OSH
18
18
37
37
LOAD
5
3
(pF)
I
µA
IL
10
10
10
10
1
4
I
µA
IH
10
10
10
10
2
4

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