AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 134

• Manufacturer Part Number: AGLN030V2-ZVQG100
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN030V2-ZVQG100

• Processor Series: AGLN030
• Core: IP Core
• Number Of Macrocells: 256
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 77
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 30 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4- 2
Revision
Revision 10 (cont’d)
The note stating what was included in I
Quiescent Supply Current (IDD) Characteristics, IGLOO nano Shutdown
The note, "per VCCI or VJTAG bank" was removed from
Supply Current (IDD), No IGLOO nano Flash*Freeze
was changed to "I
The values in
I/O Software Settings
pin) – Default I/O Software Settings1
information was added.
The following tables were updated with current available information. The
equivalent software default drive strength option was added.
Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings
Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings
Table 2-28 • I/O Output Buffer Maximum Resistances 1
Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances
Table 2-30 • I/O Short Currents IOSH/IOSL
Timing tables in the
tables for 3.3 V and 1.2 V LVCMOS wide range.
Table 2-40 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3
V Wide Range
Table 2-63 • Minimum and Maximum DC Input and Output Levels
Table 2-67 • Minimum and Maximum DC Input and Output Levels
The formulas in the notes to
Resistances
The text introducing
was revised to state six months at 100° instead of three months at 110° for
reliability concerns. The row for 110° was removed from the table.
The following sentence was deleted from the
24916): "It uses a 5-V tolerant input buffer and push-pull output buffer."
The F
Specifications" section
supported for AGLN010, AGLN015, and AGLN020.
Tables in the
information available.
Table 2-101 • IGLOO nano CCC/PLL Specification
CCC/PLL Specification
Tables in the SRAM
Characteristics" section
Table 3-3 • TRST and TCK Pull-Down Recommendations
A note was added to the
AGLN125, AGLN125Z, AGLN250, and AGLN250Z indicating that pins F1 and F2
must be grounded (SAR 25007).
A note was added to the
and AGLN060Z stating that bus hold is not available for pin H7 or pin 45 (SAR
24079).
DDRIMAX
were revised (SAR 21348).
"Global Tree Timing Characteristics" section
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default
and F
DD
= N
Table 2-31 • Duration of Short Circuit Event before Failure
DDOMAX
"Single-Ended I/O Characteristics"
and
(SAR 23919). A note was added stating that DDR is not
were revised (SAR 79390).
were updated with new information available.
BANKS
"81-Pin CS"
"Timing Characteristics" section
Table 2-14 • Summary of I/O Output Buffer Power (per
"81-Pin CS"
values were added to tables in the
* I
R ev isio n 1 1
CCI
Table 2-29 • I/O Weak Pull-Up/Pull-Down
Changes
and
+ I
CCA
"100-Pin VQFP"
pin tables for AGLN060, AGLN060Z,
were updated. Wide range support
DD
."
was removed from
"2.5 V LVCMOS" section
and
Mode1. The note giving I
Table 2-102 • IGLOO nano
is new.
pin tables for AGLN060
Table 2-12 • Quiescent
were updated with new
section, including new
and FIFO
(new)
"DDR Module
Table 2-11 •
"Timing
Mode.
(SAR
DD
3-9,
through
through
Page
2-70,
2-77,
2-19
2-40
2-24
2-25
2-32
2-51
2-64
2-71
2-84
3-14
3-9,
2-8
2-9
3-5
3-24