AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 53

• Manufacturer Part Number: AGLN030V2-ZVQG100
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN030V2-ZVQG100

• Processor Series: AGLN030
• Core: IP Core
• Number Of Macrocells: 256
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 77
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 30 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-63 • Minimum and Maximum DC Input and Output Levels
Figure 2-11 • AC Loading
Table 2-64 • 1.2 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-65 • 1.2 V LVCMOS Low Slew
Table 2-66 • 1.2 V LVCMOS High Slew
1.2 V
LVCMOS
Drive
Strength
1 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input LOW (V)
0
*
Drive Strength
1 mA
Note:
Drive Strength
1 mA
Note:
Measuring point = Vtrip. See
current is larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Min.
–0.3
V
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V
applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Timing Characteristics
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Applies to 1.2 V DC Core Voltage
Test Point
Datapath
0.35 * VCCI 0.65 * VCCI
VIL
Speed Grade
Speed Grade
Max.
V
STD
STD
Table 2-23 on page 2-20
5 pF
Min.
Input HIGH (V)
t
V
DOUT
1.55
t
DOUT
1.55
VIH
1.2
8.30
t
3.50 0.26 1.56
Max.
Enable Path
DP
t
3.6
Test Point
DP
V
J
J
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
0.26 1.56
t
t
R = 1 k
DIN
DIN
0.25 * VCCI
for a complete table of trip points.
R ev i si o n 1 1
Max.
VOL
V
t
t
PY
PY
Measuring Point* (V)
R to VCCI for t
R to GND for t
t
2.27
35 pF for t
5 pF for t
t
2.27
PYS
PYS
0.75 * VCCI
VOH
0.6
Min.
V
Table 2-6 on page 2-6
Table 2-6 on page 2-6
t
t
1.10
EOUT
EOUT
1.10
HZ
ZH
/ t
mA mA
I
/ t
7.97 7.54
OL
3.37 3.10
1
IGLOO nano Low Power Flash FPGAs
t
LZ
LZ
HZ
t
ZL
ZL
ZHS
/ t
I
/ t
OH
1
ZL
/ t
ZH
t
t
ZH
ZH
/ t
ZL
Max.
/ t
mA
I
OSL
10
ZLS
/ t
ZHS
2.56 2.55
3
ZLS
2.55 2.66
t
for derating values.
for derating values.
C
t
LZ
LZ
LOAD
Max.
I
mA
OSH
5
13
t
t
(pF)
HZ
HZ
3
µA
I
IL
10
Units
Units
1
4
ns
ns
I
µA
2- 39
IH
10
2
4