AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 24

• Manufacturer Part Number: AGLN030V2-ZVQG100
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN030V2-ZVQG100

• Processor Series: AGLN030
• Core: IP Core
• Number Of Macrocells: 256
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 77
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 30 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO nano DC and Switching Characteristics
Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices
Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices
2- 10
Parameter
PAC1
PAC2
PAC3
PAC4
PAC5
PAC6
PAC7
PAC8
PAC9
PAC10
PAC11
PAC12
PAC13
Parameter
PDC1
PDC2
PDC3
PDC4
PDC5
Notes:
1. Minimum contribution of the PLL when running at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator
or the SmartPower tool in Actel Libero
1
Array static power in Active mode
Array static power in Static (Idle)
mode
Array static power in Flash*Freeze
mode
Static PLL contribution
Bank quiescent power
(VCCI-dependent)
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
Clock contribution of a VersaTile
used as a sequential module
First contribution of a VersaTile used
as a sequential module
Second contribution of a VersaTile
used as a sequential module
Contribution of a VersaTile used as
a combinatorial module
Average contribution of a routing net
Contribution of an I/O input pin
(standard-dependent)
Contribution of an I/O output pin
(standard-dependent)
Average contribution of a RAM block
during a read operation
Average contribution of a RAM block
during a write operation
Dynamic contribution for PLL
Power Consumption of Various Internal Resources
For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage
For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage
Definition
Definition
2
®
Integrated Design Environment (IDE).
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
4.421
2.704
1.496
0.152
R ev i sio n 1 1
Device Specific Dynamic Power (µW/MHz)
4.493
1.976
1.504
0.153
25.00
30.00
1.84
2.70
Device -Specific Static Power (mW)
See
See
See
See
See
Table 2-13 on page
Table 2-12 on page 2-8
Table 2-12 on page 2-8
Table 2-12 on page 2-8
Table 2-9 on page 2-7
2.700
1.982
1.511
0.153
See
Table
0.057
0.207
0.17
0.7
2-14.
4.002
1.346
0.148
0
2-9.
4.002
1.346
0.148
N/A
N/A
N/A
N/A
0
2.633
1.340
0.143
0