AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 25

• Manufacturer Part Number: AGLN030V2-ZVQG100
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN030V2-ZVQG100

• Processor Series: AGLN030
• Core: IP Core
• Number Of Macrocells: 256
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 77
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 30 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices
Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices
Parameter
PAC1
PAC2
PAC3
PAC4
PAC5
PAC6
PAC7
PAC8
PAC9
PAC10
PAC11
PAC12
PAC13
Parameter
PDC1
PDC2
PDC3
PDC4
PDC5
Notes:
1. Minimum contribution of the PLL when running at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator
or the SmartPower tool in Actel Libero IDE.
1
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
Clock contribution of a VersaTile used
as a sequential module
First contribution of a VersaTile used
as a sequential module
Second contribution of a VersaTile
used as a sequential module
Contribution of a VersaTile used as a
combinatorial module
Average contribution of a routing net
Contribution of an I/O input pin
(standard-dependent)
Contribution of an I/O output pin
(standard-dependent)
Average contribution of a RAM block
during a read operation
Average contribution of a RAM block
during a write operation
Dynamic contribution for PLL
Array static power in Active mode
Array static power in Static (Idle)
mode
Array static power in Flash*Freeze
mode
Static PLL contribution
Bank quiescent power
(VCCI-dependent)
For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage
For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage
Definition
Definition
2
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
2.829
1.731
0.957
0.098
R ev i si o n 1 1
Device-Specific Dynamic Power (µW/MHz)
0.90
Device-Specific Static Power (mW)
25.00
30.00
2.875
1.265
0.963
0.098
2.10
See
See
See
See
See
See
Table 2-12 on page 2-8
Table 2-12 on page 2-8
Table 2-12 on page 2-8
Table 2-9 on page 2-7
Table 2-13 on page 2-9
Table 2-14 on page 2-9
1.728
1.268
0.967
0.098
0.045
0.186
0.11
0.45
IGLOO nano Low Power Flash FPGAs
2.562
0.862
0.094
0
2.562
0.862
0.094
N/A
N/A
N/A
N/A
0
1.685
0.858
0.091
0
2- 11