AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 137

• Manufacturer Part Number: AGLN030V2-ZVQG100
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN030V2-ZVQG100

• Processor Series: AGLN030
• Core: IP Core
• Number Of Macrocells: 256
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 77
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 30 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
Revision 1 (cont’d)
Revision 0 (Oct 2008)
Product Brief Advance
v0.2
The
Note 2 for the
changed to "The die attach paddle of the package is tied to ground (GND)."
The
corner instead of the upper right corner.
The following tables and sections were updated to add the UC81 and CS81
packages for AGL030:
"IGLOO nano Devices"
"I/Os Per Package"
"IGLOO nano Product Available in the Z Feature Grade"
"Temperature Grade Offerings"
The
table note 4: "For nano devices, the VQ100 package is offered in both leaded and
RoHS-compliant versions. All other packages are RoHS-compliant only."
The
to remove QN100 for AGLN250.
The device architecture figures,
with Two I/O Banks (AGLN060, AGLN125)
Architecture Overview with Four I/O Banks
IGLOO Device Architecture Overview with Two I/O Banks and No RAM
(AGLN010 and AGLN030)
The
AGLN020 and smaller devices.
The
about IGLOO nano devices supporting double-data-rate applications.
"48-Pin QFN"
"100-Pin VQFP"
"IGLOO nano Product Available in the Z Feature Grade" section
"PLL and CCC" section
"I/Os with Advanced I/O Standards" section
"I/Os Per Package"
"48-Pin
pin diagram was revised.
pin diagram was revised to move the pin IDs to the upper left
QFN",
table was updated to add the following information to
is new.
was revised to include information about CCC-GLs in
"68-Pin
Figure 1-3 • IGLOO Device Architecture Overview
R ev i si o n 1 1
Changes
QFN", and
(AGLN250), were revised.
through
"100-Pin QFN"
was revised to add information
Figure 1-4 • IGLOO Device
IGLOO nano Low Power Flash FPGAs
pin diagrams was
was updated
Figure 1-1 •
through
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