AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 8

• Manufacturer Part Number: AGLN030V2-ZVQG100
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN030V2-ZVQG100

• Processor Series: AGLN030
• Core: IP Core
• Number Of Macrocells: 256
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 77
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 30 K
• Package / Case: VQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO nano Device Overview
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IGLOO nano devices also have low dynamic power consumption to further maximize power savings;
power is reduced even further by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO nano device the lowest total system power offered by any FPGA.
Security
Nonvolatile, flash-based IGLOO nano devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. IGLOO nano devices incorporate FlashLock, which provides
a unique combination of reprogrammability and design security without external overhead, advantages
that only an FPGA with nonvolatile flash programming can offer.
IGLOO nano devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed
intellectual property and configuration data. In addition, all FlashROM data in IGLOO nano devices can
be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption
standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and
replaces the 1977 DES standard. IGLOO nano devices have a built-in AES decryption engine and a
flash-based AES key that make them the most comprehensive programmable logic device security
solution available today. IGLOO nano devices with AES-based security allow for secure, remote field
updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands
of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOO nano
device cannot be read back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent component of IGLOO nano devices. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. IGLOO nano devices, with FlashLock and AES security, are
unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected
and secure, making remote ISP possible. An IGLOO nano device provides the most impenetrable
security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO nano
FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load
device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and
system reliability.
Live at Power-Up
Actel flash-based IGLOO nano devices support Level 0 of the LAPU classification standard. This feature
helps in system component initialization, execution of critical tasks before the processor wakes up, setup
and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature
of flash-based IGLOO nano devices greatly simplifies total system design and reduces total system cost,
often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in
system power will not corrupt the IGLOO nano device's flash configuration, and unlike SRAM-based
FPGAs, the device will not have to be reloaded when system power is restored. This enables the
reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout
detection, and clock generator devices from the PCB design. Flash-based IGLOO nano devices simplify
total system design and reduce cost and design risk while increasing system reliability and improving
system initialization time.
IGLOO nano flash FPGAs enable the user to quickly enter and exit Flash*Freeze mode. This is done
almost instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike
SRAM-based FPGAs, the device does not need to reload configuration and design state from external
memory components; instead it retains all necessary information to resume operation immediately.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based IGLOO nano devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the programming
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote
in-system reprogramming to support future design iterations and field upgrades with confidence that
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