AGLN030V2-ZVQG100 Actel, AGLN030V2-ZVQG100 Datasheet - Page 51

FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano

AGLN030V2-ZVQG100

Manufacturer Part Number
AGLN030V2-ZVQG100
Description
FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
Manufacturer
Actel
Datasheet

Specifications of AGLN030V2-ZVQG100

Processor Series
AGLN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
77
Supply Voltage (max)
1.5 V
Supply Current
6 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
30 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGLN030V2-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGLN030V2-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-57 • Minimum and Maximum DC Input and Output Levels
Figure 2-10 • AC Loading
Table 2-58 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
1.5 V
LVCMOS
Drive
Strength
2 mA
Notes:
1. I
2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input LOW (V)
0
*
Measuring point = Vtrip. See
current is larger when operating outside recommended ranges.
IL
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
Min.
–0.3 0.35 * VCCI 0.65 * VCCI
V
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Test Point
Datapath
VIL
Max.
V
Table 2-23 on page 2-20
Min.
5 pF
Input HIGH (V)
V
VIH
1.5
Max.
3.6
Enable Path
V
Test Point
0.25 * VCCI 0.75 * VCCI
R = 1 k
Max.
VOL
for a complete table of trip points.
R ev i si o n 1 1
V
Measuring Point* (V)
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
VOH
Min.
0.75
V
HZ
ZH
mA mA
I
OL
/ t
2
/ t
IGLOO nano Low Power Flash FPGAs
LZ
LZ
HZ
I
ZHS
OH
2
/ t
/ t
ZL
/ t
ZH
Max.
mA
I
OSL
/ t
ZL
13
/ t
ZLS
/ t
3
ZHS
ZLS
C
LOAD
Max.
mA
I
OSH
16
5
3
(pF)
I
µA
IL
10 10
1
4
I
µA
2- 37
IH
2
4

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