LAN9118-MD SMSC, LAN9118-MD Datasheet - Page 11

• Manufacturer Part Number: LAN9118-MD
• Description: Ethernet ICs HiPerfrm Sngl-Chip 10/100 Ethrnt
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9118-MD

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
1.1
1.2
1.3
Wakup Indicator
SRAM I/F
PME
FIFO_SEL
IRQ
This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal
Block Diagram".
The LAN9118 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY
can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in
either full or half duplex configurations. The PHY block includes auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
The transmit and receive data paths are separate within the MAC allowing the highest performance
especially in full duplex mode. The data paths connect to the PIO interface Function via separate
busses to increase performance. Payload data as well as transmit and receive status is passed on
these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is
accessible from the host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media
Independent Interface) port internal to the LAN9118. The MAC CSR's also provides a mechanism for
accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive
FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly
accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and
the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer
can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working
buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX
Internal Block Overview
10/100 Ethernet PHY
10/100 Ethernet MAC
Host Bus Interface
PIO Controller
Management
Controller
GP Timer
Interrupt
Power
(HBI)
Figure 1.2 Internal Block Diagram
Configurable RX FIFO
Configurable TX FIFO
RX Status FIFO
TX Status FIFO
Core Regulator
2kB to 14kB
2kB to 14kB
3.3V to 1.8V
DATASHEET
+3.3V
11
PLL
25MHz
Ethernet
Buffer - 128 bytes
Buffer - 2K bytes
MIL - RX Elastic
MIL - TX Elastic
10/100
MAC
PLL Regulator
3.3V to 1.8V
+3.3V
Ethernet
10/100
(Optional)
EEPROM
EEPROM
Controller
PHY
Revision 1.5 (07-11-08)
LAN