LAN9118-MD SMSC, LAN9118-MD Datasheet - Page 84

• Manufacturer Part Number: LAN9118-MD
• Description: Ethernet ICs HiPerfrm Sngl-Chip 10/100 Ethrnt
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9118-MD

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.5 (07-11-08)
5.3.14
30:28
26:24
22:20
18:16
15:11
Bits
10:8
7:5
31
27
23
19
Reserved
LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output.
When cleared low, the pin functions as a GPIO signal.
Reserved
GPIO Interrupt Polarity 0-2 (GPIO_INT_POL). When set high, a high logic
level on the corresponding GPIO pin will set the corresponding INT_STS
register bit. When cleared low, a low logic level on the corresponding GPIO
pin will set the corresponding INT_STS register bit.
GPIO Interrupts must also be enabled in GPIOx_INT_EN in the INT_EN
register.
Note:
Reserved
EEPROM Enable (EEPR_EN). The value of this field determines the function
of the external EEDIO and EECLK:
Please refer to
Note:
Reserved
GPIO Buffer Type 0-2 (GPIOBUFn). When set, the output buffer for the
corresponding GPIO signal is configured as a push/pull driver. When cleared,
the corresponding GPIO set configured as an open-drain driver.
Reserved
GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO
as output. When cleared the GPIO is enabled as an input.
Reserved
LED1/GPIO0 – bit 28
LED2/GPIO1 – bit 29
LED3/GPIO2 – bit 30
GPIO0 – bit 24
GPIO1 – bit 25
GPIO2 – bit 26
GPIO0 – bit 16
GPIO1 – bit 17
GPIO2 – bit 18
GPIO0 – bit 8
GPIO1 – bit 9
GPIO2 – bit 10
GPIO_CFG—General Purpose IO Configuration Register
This register configures the GPIO and LED functions.
Offset:
GPIO inputs must be active for greater than 40nS to be recognized
as interrupt inputs.
The host must not change the function of the EEDIO and EECLK
pins when an EEPROM read or write cycle is in progress. Do not
use reserved settings.
Table 5.4
for the EEPROM Enable bit function definitions.
Description
88h
DATASHEET
84
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
32 bits
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
SMSC LAN9118
Default
Datasheet
0000
000
000
000
000
-
-
-
-
-
-