LAN9118-MD SMSC, LAN9118-MD Datasheet - Page 98

• Manufacturer Part Number: LAN9118-MD
• Description: Ethernet ICs HiPerfrm Sngl-Chip 10/100 Ethrnt
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9118-MD

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.5 (07-11-08)
5.4.3
BITS
31-0
EEPROM ADDRESS
Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the
LAN9118 device. The content of this field is undefined until loaded from the EEPROM at power-on.
The host can update the contents of this field after the initialization process has completed.
ADDRL—MAC Address Low Register
The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])
is loaded from address 0x01 of the EEPROM. The most significant byte of this register is loaded from
address 0x04 of the EEPROM. Please refer to
Table 5.7
reception of the Ethernet physical address. Also shown is the correlation between the EEPROM
addresses and ADDRL and ADDRH registers.
As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and
ADDRH registers would be programmed as shown in
load this configuration from the EEPROM are also shown.
Note: By convention, the left most byte of the Ethernet address (in this example 0x12) is the most
0x01
0x02
0x03
0x04
0x05
0x06
Offset:
Default Value:
significant byte and is transmitted/received first.
below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the
Figure 5.2 Example ADDRL, ADDRH and EEPROM Setup
Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering
31
31
0x78
xx
24
24
23
23
0x56
xx
ADDRH
ADDRL
16
16
3
FFFFFFFFh
15
15
ADDRL[23:16]
ADDRL[31:24]
ADDRH[15:8]
ADDRL[15:8]
DATASHEET
ADDRH[7:0]
ADDRL[7:0]
0xBC
0x34
ADDRN
8
8
DESCRIPTION
98
7
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
7
0x9A
0x12
Section 4.6
0
Attribute:
Size:
0
Figure
for more information on the EEPROM.
5.2. The values required to automatically
0x06
0x05
0x04
0x03
0x02
0x01
0x00
ORDER OF RECEPTION ON
EEPROM
R/W
32 bits
0xBC
0x9A
0xA5
0x78
0x56
0x34
0x12
ETHERNET
2
3
1
4
5
6
nd
rd
th
th
th
st
SMSC LAN9118
Datasheet