MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 118

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Figure 41: Refresh Mode
SELF REFRESH
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
DQS, DQS# 4
Command
Address
BA[2:0]
DM 4
DQ 4
CK#
CKE
A10
CK
NOP 1
T0
Notes:
One bank
All banks
Bank(s) 3
SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in self refresh mode, the DRAM retains data without
external clocking. Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency within the allowed synchronous oper-
ating range (see Input Clock Frequency Change (page 123)). All power supply inputs
(including V
during self refresh mode operation. All power supply inputs (including V
V
mode operation. V
certain conditions:
• V
• V
• The first WRITE operation may not occur earlier than 512 clocks after V
• All other self refresh mode exit timing requirements are met
PRE
T1
REFDQ
1. NOP commands are shown for ease of illustration; other valid commands may be possi-
2. The second REFRESH is not required but depicts two back-to-back REFRESH commands.
3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
5. Only NOP and DES commands are allowed after a REFRESH command and until
SS
REFDQ
ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH
commands, but may be inactive at other times (see Power-Down Mode (page 179)).
bank is active (must precharge all active banks).
(MIN) is satisfied.
< V
t CK
) must be maintained at valid levels upon entry/exit and during self refresh
REFDQ
is valid and stable prior to CKE going back HIGH
NOP 1
T2
REFCA
t CH
< V
t RP
t CL
and V
DD
REFDQ
NOP 1
T3
is maintained
REFDQ
may float or not drive V
118
REF
) must be maintained at valid levels upon entry/exit and
T4
t RFC (MIN)
Valid 5
NOP 5
Ta0
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x4, x8, x16 DDR3 SDRAM
REF 2
Ta1
DDQ
/2 while in self refresh mode under
Valid 5
NOP 5
Tb0
Indicates A Break in
Time Scale
© 2006 Micron Technology, Inc. All rights reserved.
t RFC 2
Valid 5
NOP 5
Tb1
REFCA
Commands
REFDQ
Don’t Care
Tb2
ACT
RA
RA
BA
and
is valid
t
RFC