MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 119

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

DLL Disable Mode
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
If the DLL is disabled by the mode register (MR1[0] can be switched during initialization
or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal
mode with a few notable exceptions:
• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS
• DLL disable mode affects the read data clock-to-data strobe relationship (
• In normal operation (DLL on),
The ODT feature is not supported during DLL disable mode (including dynamic ODT).
The ODT resistors must be disabled by continuously registering the ODT ball LOW by
programming R
mode.
Specific steps must be followed to switch between the DLL enable and DLL disable
modes due to a gap in the allowed clock rates between the two modes (
and
this clock rate gap is during self refresh mode. Thus, the required procedure for switch-
ing from the DLL enable mode to the DLL disable mode is to change frequency during
self refresh:
WRITE latency (CWL = 6).
but not the read data-to-data strobe relationship (
needed to line the read data up with the controller time domain when the DLL is disa-
bled.
cles after the READ command. In DLL disable mode,
after the READ command. Additionally, with the DLL disabled, the value of
could be larger than
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
2. Enter self refresh mode after
3. After
4. Self refresh may be exited when the clock is stable with the new frequency for
5. The DRAM will be ready for its next command in the DLL disable mode after the
t
CK [DLL disable] MIN, respectively). The only time the clock is allowed to cross
is turned off, and R
t
greater of
with appropriate timings met.
CKSRX. After
t
CKSRE is satisfied, change the frequency to the desired clock rate.
t
TT,nom
MRD or
t
XS is satisfied, update the mode registers with appropriate values.
MR1[9, 6, 2] and R
t
CK.
TT,nom
t
MOD has been satisfied. A ZQCL command should be issued
119
and R
t
DQSCK starts from the rising clock edge AL + CL cy-
t
MOD has been satisfied.
TT(WR)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
TT(WR)
are High-Z), set MR1[0] to 1 to disable the DLL.
2Gb: x4, x8, x16 DDR3 SDRAM
MR2[10, 9] to 0 while in the DLL disable
t
DQSQ,
t
DQSCK starts AL + CL - 1 cycles
t
QH). Special attention is
© 2006 Micron Technology, Inc. All rights reserved.
t
CK [AVG] MAX
Commands
t
DQSCK),
t
DQSCK