MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 123

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Input Clock Frequency Change
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
When the DDR3 SDRAM is initialized, it requires the clock to be stable during most nor-
mal states of operation. This means that after the clock frequency has been set to the
stable state, the clock period is not allowed to deviate except what is allowed for by the
clock jitter and spread spectrum clocking (SSC) specifications.
The input clock frequency can be changed from one stable clock rate to another under
two conditions: self refresh mode and precharge power-down mode. Outside of these
two modes, it is illegal to change the clock frequency. For the self refresh mode condi-
tion, when the DDR3 SDRAM has been successfully placed into self refresh mode and
t
clock becomes a “Don’t Care,” changing the clock frequency is permissible, provided
the new clock frequency is stable prior to
fresh mode for the sole purpose of changing the clock frequency, the self refresh entry
and exit specifications must still be met.
The precharge power-down mode condition is when the DDR3 SDRAM is in precharge
power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a
logic LOW or R
R
and CKE must be at a logic LOW. A minimum of
LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency
is allowed to change only within the minimum and maximum operating frequency speci-
fied for the particular speed grade (
clock frequency change, CKE must be held at a stable LOW level. When the input clock
frequency is changed, a stable clock must be provided to the DRAM
charge power-down may be exited. After precharge power-down is exited and
been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequen-
cy, additional MRS commands may need to be issued. During the DLL lock time,
R
ready to operate with a new clock frequency.
CKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the
TT,nom
TT,nom
and R
and R
TT(WR)
TT(WR)
TT,nom
are in an off state prior to entering precharge power-down mode,
must remain in an off state. After the DLL lock time, the DRAM is
and R
TT(WR)
123
must be disabled via MR1 and MR2. This ensures
t
CK [AVG] MIN to
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
CKSRX. When entering and exiting self re-
Input Clock Frequency Change
2Gb: x4, x8, x16 DDR3 SDRAM
t
CKSRE must occur after CKE goes
t
CK [AVG] MAX). During the input
© 2006 Micron Technology, Inc. All rights reserved.
t
CKSRX before pre-
t
XP has