MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 190

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Table 82: Truth Table – ODT (Nominal)
Note 1 applies to the entire table
Table 83: ODT Parameter
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
ODTL off
ODTL on
Symbol
t
t
ODTH4
ODTH8
AONPD
AOFPD
t
t
AON
AOF
MR1[9, 6, 2]
110 and 111
000–101
000–101
000
000
ODT minimum HIGH time after ODT
ODT turn-off relative to ODTL off
ODT asynchronous turn off delay
ODT turn-on relative to ODTL on
ODT asynchronous turn on delay
ODT synchronous turn off delay
ODT synchronous turn on delay
ODT minimum HIGH time after
assertion or write (BC4)
Notes:
ODT Pin
Description
completion
completion
write (BL8)
0
1
0
1
X
Nominal ODT resistance R
(MR1) Definition. The R
mentioned. DDR3 SDRAM supports multiple R
can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. R
the DRAM is initialized, calibrated, and not performing read access or when it is not in
self refresh mode.
Write accesses use R
ing writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 85 (page 192)). ODT
timings are summarized in Table 83 (page 190), as well as listed in Table 56 (page 78).
Examples of nominal ODT timing are shown in conjunction with the synchronous
mode of operation in Synchronous ODT Mode (page 196).
1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 191) when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal
3. ODT must be disabled during reads. The R
to have it off during writes.
ic ODT is applicable if enabled.
R
TT,nom
DRAM Termination State
R
R
R
R
TT,nom
TT,nom
TT,nom
TT,nom
reserved, ODT on or off
disabled, ODT off
TT,nom
enabled, ODT off
disabled, ODT on
enabled, ODT on
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
Completion of ODTL
Completion of ODTL
or write registration
Write registration
with ODT HIGH
with ODT HIGH
TT,nom
Begins at
TT,nom
if dynamic ODT (R
190
off
on
termination value applies to the output pins previously
is defined by MR1[9, 6, 2], as shown in Mode Register 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
TT,nom
ODT registered
ODT registered
R
R
Defined to
TT,nom
TT,on
TT,off
TT(WR)
Any valid except self refresh, read
Any valid except self refresh, read
2Gb: x4, x8, x16 DDR3 SDRAM
TT,nom
R
R
R
R
LOW
LOW
termination is allowed any time after
TT,off
TT,off
TT,on
TT,on
±
±
value is restricted during writes. Dynam-
t
t
AON
) is disabled. If R
AOF
On-Die Termination (ODT)
values based on RZQ/n where n
DRAM State
Any valid
Any valid
See Table 56 (page 78)
Illegal
Definition for All
DDR3 Speed Bins
© 2006 Micron Technology, Inc. All rights reserved.
0.5
CWL + AL - 2
CWL + AL - 2
t
CK ± 0.2
4
6
1–9
1–9
TT,nom
t
t
CK
CK
t
CK
is used dur-
Notes
Units
t
t
t
t
t
CK
CK
ns
ns
CK
CK
ps
CK
2
3
2
3