PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 16

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

Pin description
Table 3.
16/128
Pin name
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PLCC52 pin description
Pin
29
28
27
25
24
23
22
21
52
51
20
19
18
7
6
5
4
3
2
Type
I/O
I/O
I/O
I/O
I/O
These pins make up port A. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7) outputs.
Inputs to the PLDs.
Latched address outputs (see
Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.
As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
D0/A16-D3/A19 in M37702M2 mode.
Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate.
These pins make up port B. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
Inputs to the PLDs.
Latched address outputs (see
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate.
PC0 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC0) output.
Input to the PLDs.
TMS input
This pin can be configured as a CMOS or Open Drain output.
PC1 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC1) output.
Input to the PLDs.
TCK input
This pin can be configured as a CMOS or Open Drain output.
PC2 pin of port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC2) output.
Input to the PLDs.
This pin can be configured as a CMOS or Open Drain output.
However, PA4-PA7 can be configured as CMOS or Open Drain outputs.
However, PB4-PB7 can be configured as CMOS or Open Drain outputs.
(2)
(2)
for the JTAG Serial Interface.
for the JTAG Serial Interface.
(1)
(continued)
Doc ID 7833 Rev 7
Table
Table
7).
7).
Description
PSD8XXFX