PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 22

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD architectural overview
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The PSD also has some bits that are configured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches
its outputs and goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD
to reduce power consumption. Please see
Table 5.
Table 6.
PC0
PC1
PC3
PC4
PC5
PC6
Primary Flash memory
Secondary Flash memory
PLD array (DPLD and CPLD)
PSD configuration
Functional block
Port C pins
JTAG SIgnals on port C
Methods for programming different functional blocks of the PSD
Doc ID 7833 Rev 7
TMS
TCK
TSTAT
TERR
TDI
TDO
Yes
Yes
Yes
Yes
programming
Section 17: Power management
JTAG
Yes
Yes
Yes
Yes
JTAG signal
programmer
Device
Yes
Yes
No
No
for more details.
PSD8XXFX
IAP