PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 63

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD8XXFX
15.6
Figure 21. Interfacing the PSD with the 80C251, with One READ input
1. The A16 and A17 connections are optional.
2. In non-Page-mode, AD7-AD0 connects to ADIO7-ADIO0.
RESET
RESET
20
13
14
15
16
17
10
35
21
11
2
4
6
9
80C251
The Intel 80C251 MCU features a user-configurable bus interface with four possible bus
configurations, as shown in
The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to
that shown in
as shown in
PSD. The A16 connection to PA0 allows for a larger address input to the PSD. The fourth
configuration is shown in
Select Enable (PSEN) is connected to CNTL2.
The 80C251 has two major operating modes: Page mode and Non-page mode. In Non-
page mode, the data is multiplexed with the lower address byte, and Address Strobe
(ALE/AS, PD0) is active in every bus cycle. In Page mode, data (D7-D0) is multiplexed with
address (A15-A8). In a bus cycle where there is a Page hit, Address Strobe (ALE/AS, PD0)
is not active and only addresses (A7-A0) are changing. The PSD supports both modes. In
Page mode, the PSD bus timing is identical to Non-Page mode except the address hold time
and setup time with respect to Address Strobe (ALE/AS, PD0) is not required. The PSD
access time is measured from address (A7-A0) valid to data in valid.
3
5
7
8
80C251SB
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
RST
EA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
X1
X2
Figure
Figure
RD/A16
PSEN
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.5
P2.6
P2.7
P2.4
ALE
WR
21. There is only one Read Strobe (PSEN) connected to CNTL1 on the
43
42
41
40
39
38
37
24
25
27
33
32
18
19
36
26
28
29
30
31
20. The second and third configurations have the same bus connection
RESET
Figure
A1
A4
AD9
AD10
AD11
AD12
AD13
AD14
ALE
RD
WR
A16
A0
A2
A3
A5
A6
A7
AD8
AD15
Table
Doc ID 7833 Rev 7
22. Read Strobe (RD) is connected to CNTL1 and Program
19.
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
46
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
47
50
49
10
48
9
8
PSD
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 ( WR )
CNTL1 ( RD )
CNTL 2(PSEN)
PD0- ALE
PD1
PD2
RESET
MCU bus interface
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
29
28
27
25
24
23
22
19
18
17
14
13
12
11
21
7
6
5
4
3
2
52
51
20
A16 1
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A17 1