PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 53

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD8XXFX
14.4
Output macrocell (OMC)
Eight of the Output macrocells (OMC) are connected to ports A and B pins and are named
as McellAB0-McellAB7. The other eight macrocells are connected to ports B and C pins and
are named as McellBC0-McellBC7. If an McellAB output is not assigned to a specific pin in
PSDabel, the macrocell Allocator block assigns it to either port A or B. The same is true for
a McellBC output on port B or C.
The Output macrocell (OMC) architecture is shown in
there are native product terms available from the AND Array, and borrowed product terms
available (if unused) from other Output macrocells (OMC). The polarity of the product term
is controlled by the XOR gate. The Output macrocell (OMC) can implement either sequential
logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the
sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and
has a feedback path to the AND Array inputs.
The flip-flop in the Output macrocell (OMC) block can be configured as a D, T, JK, or SR
type in the PSDabel program. The flip-flop’s clock, preset, and clear inputs may be driven
from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock
input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset
and clear are active high inputs. Each clear input can use up to two product terms.
Table 16.
macrocell
McellBC0
McellBC1
McellBC2
McellBC3
McellBC4
McellBC5
McellBC6
McellBC7
McellAB0
McellAB1
McellAB2
McellAB3
McellAB4
McellAB5
McellAB6
McellAB7
Output
Output macrocell port and data bit assignments
assignment
Port B0, C0
Port B1, C1
Port B2, C2
Port B3, C3
Port B4, C4
Port B5, C5
Port B6, C6
Port B7, C7
Port A0, B0
Port A1, B1
Port A2, B2
Port A3, B3
Port A4, B4
Port A5, B5
Port A6, B6
Port A7, B7
Port
Doc ID 7833 Rev 7
Table 16
Native product
terms
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
shows the macrocells and port assignment.
borrowed product
Figure
Maximum
terms
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
15. As shown in the figure,
Data bit for loading
or reading
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
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PLDS