PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 66

no-image

PSD813F2-A-70J

Manufacturer Part Number
PSD813F2-A-70J
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of PSD813F2-A-70J

Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
PLCC
Mounting
Surface Mount
Pin Count
52
Lead Free Status / RoHS Status
Compliant
MCU bus interface
15.8
Figure 24. Interfacing the PSD with a 68HC11
66/128
RESET
68HC11
Figure 24
multiplexed mode with E and R/W settings. The DPLD can be used to generate the READ
and WR signals for external devices.
17
19
18
34
33
32
43
44
45
46
47
48
49
50
52
51
8
7
2
68HC11
shows a bus interface to a 68HC11 where the PSD is configured in 8-bit
XT
EX
RESET
IRQ
XIRQ
MODB
PA0
PA1
PA2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL
MODA
PC0
R / W
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
AS
E
RESET
10
11
12
13
14
15
16
39
38
37
36
35
9
20
21
22
23
24
25
3
5
4
6
31
30
29
28
27
42
41
40
Doc ID 7833 Rev 7
E
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AS
R/ W
A10
A11
A12
A13
A14
A15
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
47
50
49
10
48
9
8
PSD
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0 (R _ W)
CNTL1(E)
CNTL 2
PD0 – AS
PD1
PD2
RESET
AD7-AD0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
AD7-AD0
PSD8XXFX
29
28
27
25
24
23
22
21
7
6
5
4
2
52
51
19
18
17
14
13
12
11
3
20
AI02884C

Related parts for PSD813F2-A-70J