PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 71

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD8XXFX
16.6
16.7
16.8
16.9
Address In mode
For MCUs that have more than 16 address signals, the higher addresses can be connected
to port A, B, C, and D. The address input can be latched in the input macrocell (IMC) by
Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equations for the
SRAM, or primary or secondary Flash memory is considered to be an address input.
Data port mode
Port A can be used as a data bus port for a MCU with a non-multiplexed address/data bus.
The Data port is connected to the data bus of the MCU. The general I/O functions are
disabled in port A if the port is configured as a Data port.
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of
port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is
enabled by setting Bit 7 of the VM register to a ’1.’
directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for
PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is tri-stated when PSEL0 or
PSEL1 is not active.
Figure 26. Peripheral I/O mode
JTAG in-system programming (ISP)
Port C is JTAG compliant, and can be used for in-system programming (ISP). You can
multiplex JTAG operations with other functions on port C because in-system programming
(ISP) is not performed in normal operating mode. For more information on the JTAG port,
see
Section 19: Programming in-circuit using the JTAG serial
RD
PSEL0
PSEL1
WR
VM REGISTER BIT 7
Doc ID 7833 Rev 7
PSEL
DATA BUS
D0 - D7
Figure 26
shows how port A acts as a bi-
interface.
PA0 - PA7
I/O ports
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