PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 77

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD8XXFX
16.23
Port D pins can be configured in PSDsoft Express as input pins for other dedicated
functions:
●
●
●
Figure 29. Port D structure
External Chip Select
The CPLD also provides three External Chip Select (ECS0-ECS2) outputs on port D pins
that can be used to select external devices. Each External Chip Select (ECS0-ECS2)
consists of one product term that can be configured active high or low. The output enable of
the pin is controlled by either the output enable product term or the Direction register (see
Figure
Address Strobe (ALE/AS, PD0)
CLKIN (PD1) as input to the macrocells flip-flops and APD counter
PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory,
SRAM and CSIOP.
30).
ECS [ 2:0 ]
WR
WR
DATA OUT
READ MUX
DIR REG.
D
D
REG.
D
B
P
Doc ID 7833 Rev 7
Q
Q
DATA OUT
DATA IN
CPLD -INPUT
OUTPUT
OUTPUT
SELECT
MUX
ENABLE PRODUCT
TERM (.OE)
PORT D PIN
AI02889
I/O ports
77/128