PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 50

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PLDS
14.2
Figure 13. DPLD logic array
50/128
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
PGR0 - PGR7
I /O PORTS (PORT A,B,C)
A [ 15:0 ]
PD [ 2:0 ] (ALE,CLKIN,CSI)
PDN (APD OUTPUT)
CNTRL [ 2:0 ] ( READ/WRITE CONTROL SIGNALS)
RESET
RD_BSY
*
Decode PLD (DPLD)
The DPLD, shown in
components. The DPLD can be used to generate the following decode signals:
●
●
●
●
●
●
8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms
each)
4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three
product terms each)
1 internal SRAM Select (RS0) signal (two product terms)
1 internal CSIOP Select (PSD Configuration register) signal
1 JTAG Select signal (enables JTAG on port C)
2 internal Peripheral Select signals
(Peripheral I/O mode).
(INPUTS)
Figure
(24)
(16)
(8)
(8)
(8)
(3)
(3)
(1)
(1)
(1)
13, is used for decoding the address for internal and external
Doc ID 7833 Rev 7
3
3
3
3
3
3
3
3
3
3
3
3
2
1
1
1
1
RS0
CSIOP
PSEL0
PSEL1
JTAGSEL
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS1
FS7
FS2
FS3
FS5
FS6
FS4
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O MODE
SELECT
8 PRIMARY FLASH
MEMORY SECTOR SELECTS
PSD8XXFX
AI02873D