PSD813F2-A-70J STMicroelectronics, PSD813F2-A-70J Datasheet - Page 65

• Manufacturer Part Number: PSD813F2-A-70J
• Manufacturer: STMicroelectronics

Specifications of PSD813F2-A-70J

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD8XXFX
15.7
Figure 23. Interfacing the PSD with the 80C51X, 8-bit data bus
RESET
80C51XA
The Philips 80C51XA MCU family supports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with
data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) are multiplexed with data bits
(D7-D0).
The 80C51XA can be configured to operate in eight-bit data mode (as shown in
The 80C51XA improves bus throughput and performance by executing burst cycles for code
fetches. In Burst mode, address A19-A4 are latched internally by the PSD, while the
80C51XA changes the A3-A0 signals to fetch up to 16 bytes of code. The PSD access time
is then measured from address A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst mode is identical to the normal bus cycle, except the address setup
and hold time with respect to Address Strobe (ALE/AS, PD0) does not apply.
10
14
15
17
35
21
20
11
13
16
6
7
9
8
80C51XA
XTAL1
XTAL2
RXD0
TXD0
RXD1
T2EX
T2
T0
RST
INT0
INT1
EA/WAIT
BUSW
TXD1
A0/WRH
RESET
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
A10D6
A11D7
A12D8
A13D9
PSEN
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
WRL
ALE
RD
A1
A2
A3
30
2
3
4
5
43
42
41
40
39
38
37
36
24
25
26
28
29
31
27
19
18
32
33
A0
A1
A2
A3
A4D0
A6D2
A7D3
A8D4
A5D1
A9D5
A10D6
A11D7
A12
A13
A14
A15
A17
A18
A19
A16
Doc ID 7833 Rev 7
PSEN
ALE
WR
RD
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A12
A13
A14
A16
A17
A15
A18
A10D6
A11D7
A19
46
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
47
50
49
10
48
8
9
PSD
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0 ( WR )
CNTL1 ( RD )
CNTL 2 (PSEN)
PD0-ALE
PD1
PD2
RESET
MCU bus interface
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB5
PB6
PB7
PB4
Figure
20
19
18
17
14
13
12
11
29
28
27
25
24
23
22
7
6
5
4
3
2
52
51
21
AI02883C
A0
A1
A2
A3
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23).