MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 113

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
10. The DES and NOP commands perform similarly.
11. The power-down mode does not perform any REFRESH operations.
12. ZQ CALIBRATION LONG is used for either ZQinit (first ZQCL command during initializa-
2. RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be
3. The state of ODT does not affect the states described in this table.
4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of
5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.”
6. See Table 70 (page 114) for additional information on CKE transition.
7. Self refresh exit is asynchronous.
8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC
9. The purpose of the NOP command is to prevent the DRAM from registering any unwan-
held HIGH during any normal operation.
four mode registers.
are defined in MR0.
ted commands. A NOP will not terminate an operation that is executing.
tion) or ZQoper (ZQCL command after initialization).
113
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2Gb: x4, x8, x16 DDR3 SDRAM
Commands – Truth Tables
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