MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 152

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ZQ CALIBRATION Operation
Figure 64: ZQ Calibration Timing (ZQCL and ZQCS)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Command
Address
ODT
CK#
A10
CKE
DQ
CK
ZQCL
1
2
3
T0
Notes:
NOP
T1
The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (R
and ODT values (R
240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to V
DDR3 SDRAM need a longer time to calibrate R
and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3
SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example of ZQ
calibration timing is shown below.
All banks must be precharged and
can be issued to the DRAM. No other activities (other than another ZQCL or ZQCS com-
mand may be issued to another DRAM) can be performed on the DRAM channel by the
controller for the duration of
helps accurately calibrate R
should disable the ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must
not allow overlap of
1. CKE must be continuously registered HIGH during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
3. All devices connected to the DQ bus should be High-Z during calibration.
t ZQ
High-Z
NOP
Ta0
init
or t ZQ
oper
NOP
Ta1
TT
t
) over process, voltage, and temperature, provided a dedicated
ZQinit,
Valid
Valid
Valid
Valid
Valid
Ta2
ON
t
152
ZQoper, or
t
ZQinit or
and ODT. After DRAM calibration is achieved, the DRAM
Activities
Valid
Valid
Valid
Valid
Valid
Ta3
t
RP must be met before ZQCL or ZQCS commands
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
ZQoper. The quiet time on the DRAM channel
t
ZQcs between ranks.
ZQCS
Tb0
1
2
3
2Gb: x4, x8, x16 DDR3 SDRAM
ON
NOP
Tb1
ZQ CALIBRATION Operation
and ODT at power-up initialization
Indicates A Break in
Time Scale
High-Z
NOP
t ZQCS
Tc0
© 2006 Micron Technology, Inc. All rights reserved.
NOP
Tc1
SSQ
Don’t Care
.
Valid
Valid
Valid
Valid
Valid
Tc2
Activ-
ities
ON
)