MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 116

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 71: READ Command Summary
WRITE
Table 72: WRITE Command Summary
PRECHARGE
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Function
READ
READ with
auto
precharge
Function
WRITE
WRITE with
auto
precharge
BL8MRS,
BL8MRS,
BC4MRS
BC4MRS
BL8MRS,
BL8MRS,
BC4OTF
BC4OTF
BC4MRS
BC4MRS
BL8OTF
BL8OTF
BC4OTF
BC4OTF
BL8OTF
BL8OTF
determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the
READ burst may not be interrupted.
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or
not auto precharge is used. The value on input A12 (if enabled in the MR) when the
WRITE command is issued determines whether BC4 (chop) or BL8 is used.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory. If the DM signal is registered HIGH,
the corresponding data inputs will be ignored and a WRITE will not be executed to that
byte/column location.
The PRECHARGE command is used to deactivate the open row in a particular bank or
in all banks. The bank(s) are available for a subsequent row access a specified time (
after the PRECHARGE command is issued, except in the case of concurrent auto pre-
Symbol
WRAPS4
WRAPS8
Symbol
RDAPS4
RDAPS8
WRAP
WRS4
WRS8
RDAP
RDS4
RDS8
WR
RD
Cycle
Prev.
Cycle
Prev.
CKE
CKE
H
H
H
H
H
H
H
H
H
H
H
H
Cycle
Next
Cycle
Next
CS# RAS# CAS# WE#
116
CS# RAS# CAS# WE#
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
Micron Technology, Inc. reserves the right to change products or specifications without notice.
L
L
L
L
L
L
L
L
L
L
L
L
2Gb: x4, x8, x16 DDR3 SDRAM
L
L
L
L
L
L
H
H
H
H
H
H
[3:0]
BA
BA
BA
BA
BA
BA
BA
[3:0]
BA
BA
BA
BA
BA
BA
BA
RFU
RFU
RFU
RFU
RFU
RFU
An
© 2006 Micron Technology, Inc. All rights reserved.
RFU
RFU
RFU
RFU
RFU
RFU
An
A12
A12
V
H
V
H
L
L
V
H
V
H
L
L
Commands
A10
A10
H
H
H
L
L
L
H
H
H
L
L
L
A[11,
A[11,
9:0]
9:0]
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
t
RP)