MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 148

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MT41J256M8DA-125:H

Manufacturer Part Number
MT41J256M8DA-125:H
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT41J256M8DA-125:H

Lead Free Status / Rohs Status
Supplier Unconfirmed
Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout
Bank address
DQS, DQS#
Command
A12/BC#
A[15:13]
A10/AP
A[1:0]
A[9:3]
A11
CK#
DQ
CK
A2
PREA
T0
1
t RP
MRS
Notes:
Ta
00
3
0
1
0
0
0
0
t MOD
READ 1
1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].
Valid
Valid
Valid
Valid
Valid
Valid
Tb
0 2
0 2
t CCD
READ 1
Valid 1
Valid
Valid
Valid
Valid
Valid
Tc0
RL
0 2
1 2
NOP
Tc1
NOP
Tc2
RL
NOP
Tc3
NOP
Tc4
NOP
Tc5
NOP
Tc6
NOP
Tc7
Tc8
NOP
Indicates A Break in
Time Scale
NOP
Tc9
t MPRR
Tc10
Valid
MRS
00
3
0
0
0
0
0
t MOD
Don’t Care
Valid
Td

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