MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 136

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Precharge Power-Down (Precharge PD)
CAS Latency (CL)
Figure 53: READ Latency
DQS, DQS#
DQS, DQS#
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Command
Command
CK#
CK#
DQ
DQ
CK
CK
READ
READ
T0
T0
Notes:
NOP
NOP
T1
T1
t
= roundup (
The precharge PD bit applies only when precharge power-down mode is being used.
When MR0[12] is set to 0, the DLL is off during precharge power-down providing a low-
er standby current mode; however,
MR0[12] is set to 1, the DLL continues to run during precharge power-down mode to
enable a faster exit of precharge power-down mode; however,
when exiting (see Power-Down Mode (page 179)).
The CL is defined by MR0[6:4], as shown in Figure 52 (page 134). CAS latency is the de-
lay, in clock cycles, between the internal READ command and the availability of the first
bit of output data. The CL can be set to 5, 6, 7, 8, 9, 10, 11, 12, or 13. DDR3 SDRAM do
not support half-clock latencies.
Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is regis-
tered at clock edge n, and the CAS latency is m clocks, the data will be available
nominally coincident with clock edge n + m. on page through Table 53 (page 75) indi-
cate the CLs supported at various operating frequencies.
WR (ns) by
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal
NOP
NOP
T2
T2
t
t
CK (ns) and rounding up a noninteger value to the next integer: WR (cycles)
WR [ns]/
AL = 0, CL = 6
NOP
NOP
T3
T3
t
CK [ns]).
t
DQSCK and nominal
AL = 0, CL = 8
136
NOP
NOP
T4
T4
t
XPDLL must be satisfied when exiting. When
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
NOP
T5
T5
t
DSDQ.
2Gb: x4, x8, x16 DDR3 SDRAM
NOP
NOP
T6
T6
Mode Register 0 (MR0)
DI
n
© 2006 Micron Technology, Inc. All rights reserved.
t
n + 1
XP must be satisfied
Transitioning Data
DI
NOP
NOP
T7
T7
n + 2
DI
n + 3
DI
NOP
NOP
T8
T8
Don’t Care
n + 4
DI
DI
n