MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 150

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 63: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble
Bank address
DQS, DQS#
Command
A12/BC#
A[15:13]
A10/AP
A[1:0]
A[9:3]
A11
CK#
DQ
CK
A2
PREA
T0
1
t RF
MRS
Notes:
Ta
00
3
0
1
0
0
0
0
t MOD
READ 1
Valid 1
1. READ with BC4 either by MRS or OTF.
2. Memory controller must drive 0 on A[1:0].
3. A2 = 1 selects upper 4 nibble bits 4 . . . 7.
4. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
Valid
Valid
Valid
Valid
Valid
Tb
0 2
1 3
t CCD
Valid 1
READ 1
Valid
Valid
Valid
Valid
Valid
Tc0
RL
0 2
0 4
Tc1
NOP
NOP
Tc2
RL
NOP
Tc3
NOP
Tc4
NOP
Tc5
NOP
Tc6
NOP
Tc7
t MPRR
Valid
MRS
Tc8
00
3
0
0
0
0
0
Indicates A Break in
Time Scale
NOP
Tc9
t MOD
Tc10
NOP
Don’t Care
Valid
Td