MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 7

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 51: Differential Output Slew Rate Definition ......................................................................................... 73
Table 52: DDR3-1066 Speed Bins ................................................................................................................... 74
Table 53: DDR3-1333 Speed Bins ................................................................................................................... 75
Table 54: DDR3-1600 Speed Bins ................................................................................................................... 76
Table 55: DDR3-1866 Speed Bins ................................................................................................................... 77
Table 56: Electrical Characteristics and AC Operating Conditions ................................................................... 78
Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions ................................... 87
Table 58: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based ....................... 97
Table 59: Derating Values for
Table 60: Derating Values for
Table 61: Derating Values for
Table 62: Derating Values for
Table 63: Minimum Required Time
Table 64: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based .................................. 105
Table 65: Derating Values for
Table 66: Derating Values for
Table 67: Derating Values for
Table 68: Required Time
Table 69: Truth Table – Command ................................................................................................................ 112
Table 70: Truth Table – CKE ......................................................................................................................... 114
Table 71: READ Command Summary ............................................................................................................ 116
Table 72: WRITE Command Summary .......................................................................................................... 116
Table 73: READ Electrical Characteristics, DLL Disable Mode ........................................................................ 122
Table 74: Write Leveling Matrix ..................................................................................................................... 126
Table 75: Burst Order ................................................................................................................................... 135
Table 76: MPR Functional Description of MR3 Bits ........................................................................................ 145
Table 77: MPR Readouts and Burst Order Bit Mapping .................................................................................. 146
Table 78: Self Refresh Temperature and Auto Self Refresh Description ........................................................... 178
Table 79: Self Refresh Mode Summary .......................................................................................................... 178
Table 80: Command to Power-Down Entry Parameters ................................................................................. 179
Table 81: Power-Down Modes ...................................................................................................................... 180
Table 82: Truth Table – ODT (Nominal) ........................................................................................................ 190
Table 83: ODT Parameter ............................................................................................................................. 190
Table 84: Dynamic ODT Specific Parameters ................................................................................................. 191
Table 85: Mode Registers for R
Table 86: Mode Registers for R
Table 87: Timing Diagrams for Dynamic ODT ............................................................................................... 192
Table 88: Synchronous ODT Parameters ....................................................................................................... 197
Table 89: Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 202
Table 90: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period .................................. 204
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
t
VAC Above V
t
t
t
t
t
t
t
IS/
IS/
IS/
IS/
DS/
DS/
DS/
TT,nom
TT(WR)
t
t
t
t
IH – AC175/DC100-Based ........................................................................... 98
IH – AC150/DC100-Based ........................................................................... 98
IH – AC135/DC100-Based ........................................................................... 99
IH – AC125/DC100-Based ........................................................................... 99
t
t
t
DH – AC175/DC100-Based ....................................................................... 106
DH – AC150/DC100-Based ....................................................................... 106
DH – AC135/DC100-Based ....................................................................... 107
t
VAC Above V
............................................................................................................. 192
............................................................................................................. 192
IH(AC)
(Below V
IH(AC)
IL(AC)
for Valid Transition ................................................... 100
7
) for Valid Transition ............................................. 107
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x4, x8, x16 DDR3 SDRAM
© 2006 Micron Technology, Inc. All rights reserved.