MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 120

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 42: DLL Enable Mode to DLL Disable Mode
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Command
ODT 9
CKE
CK#
CK
6
MRS 2
T0
Notes:
t MOD
NOP
T1
A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 43 (page 121)).
1. Any valid command.
2. Disable DLL by setting MR1[0] to 1.
3. Enter SELF REFRESH.
4. Exit SELF REFRESH.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, R
7. Change frequency.
8. Clock must be stable
9. Static LOW in the case that R
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
2. After
3. Self refresh may be exited when the clock is stable with the new frequency for
4. After another
5. The DRAM will be ready for its next command in the DLL enable mode after the
SRE 3
is turned off, and R
t
ues. At a minimum, set MR1[0] to 0 to enable the DLL. Wait
to 1 to enable DLL RESET.
with the appropriate values.
greater of
mand or function requiring a locked DLL, a delay of
be satisfied. A ZQCL command should be issued with the appropriate timings met.
Ta0
CKSRX. After
t
CKSRE is satisfied, change the frequency to the new clock rate.
t CKSRE
NOP
Ta1
t
MRD or
t
t
MRD delay is satisfied, then update the remaining mode registers
XS is satisfied, update the mode registers with the appropriate val-
t CKESR
Tb0
TT,nom
t
t
MOD has been satisfied. However, before applying any com-
CKSRX.
7
120
and R
TT,nom
TT
Tc0
is in the High-Z state.
t CKSRX 8
TT(WR)
or R
Micron Technology, Inc. reserves the right to change products or specifications without notice.
SRX 4
Td0
TT(WR)
are High-Z), enter self refresh mode.
2Gb: x4, x8, x16 DDR3 SDRAM
is enabled; otherwise, static LOW or HIGH.
NOP
Td1
t XS
Indicates A Break in
Time Scale
t
DLLK after DLL RESET must
MRS 5
Te0
© 2006 Micron Technology, Inc. All rights reserved.
t
MRD, then set MR0[8]
t MOD
NOP
Te1
Commands
Don’t Care
Valid 1
Valid 1
Valid 1
Tf0