MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 168

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 84: WRITE Burst
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Command 1
DQS, DQS#
DQS, DQS#
DQS, DQS#
Address 2
DQ 3
DQ 3
DQ 3
CK#
CK
t DQSS (NOM)
t DQSS (MAX)
t DQSS (MIN)
WRITE
Bank,
Col n
T0
NOP
T1
Notes:
WL = AL + CWL
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5.
6.
NOP
T2
these times.
the WRITE command at T0.
t
t
ly ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
DQSS must be met at each rising clock edge.
WPST is usually depicted as ending at the crossing of DQS, DQS#; however,
NOP
T3
t DQSH
NOP
T4
t DQSH
t WPRE
t DQSH
t WPRE
t DQSL
168
t DQSL
t WPRE
t DQSS t DSH
t DSS
DI
n
t DSS
t DQSH
t DQSL
NOP
DI
T5
n
t DQSS
t DQSH
t DSH
n + 1
DI
DI
n
t DQSH
t DQSL
n + 1
DI
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t DQSL
t DSS
n + 2
n + 1
DI
DI
t DSS
t DQSH
t DQSL
NOP
n + 2
T6
DI
t DSH
t DQSH
t DSH
n + 3
n + 2
DI
DI
t DQSH
t DQSL
2Gb: x4, x8, x16 DDR3 SDRAM
n + 3
DI
t DQSL
n + 4
t DSS
n + 3
DI
DI
t DSS
t DQSH
t DQSL
n + 4
NOP
T7
DI
t DSH
t DQSH
t DSH
n + 4
n + 5
DI
DI
t DQSH
t DQSL
n + 5
DI
t DQSL
t DSS
n + 6
n + 5
DI
DI
t DSS
t DQSH
t DQSL
n + 6
NOP
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T8
DI
t DSH
t DQSH
t DSH
n + 7
n + 6
DI
DI
WRITE Operation
t DQSH
t WPST
t DQSL
n + 7
Transitioning Data
DI
t DQSL
t WPST
t DSS
n + 7
DI
t DSS
t WPST
t DQSL
NOP
T9
t
WPST actual-
Don’t Care
T10
NOP