MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 139

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

On-Die Termination
WRITE LEVELING
POSTED CAS ADDITIVE Latency
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
functions share the same ball. When the TDQS function is enabled via the mode regis-
ter, the DM function is not supported. When the TDQS function is disabled, the DM
function is provided, and the TDQS# ball is not used. The TDQS function is available in
the x8 DDR3 SDRAM configuration only and must be disabled via the mode register for
the x4 and x16 configurations.
ODT resistance R
termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3
supports multiple R
12 and RZQ is 240Ω.
Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain
off during a READ burst.R
tialized, calibrated, and not performing read access, or when it is not in self refresh
mode. Additionally, write accesses with dynamic ODT enabled (R
placesR
The actual effective termination, R
nonlinearity of the termination. For R
nation (ODT) (page 189)).
The ODT feature is designed to improve signal integrity of the memory channel by ena-
bling the DDR3 SDRAM controller to independently turn on/off ODT for any or all
devices. The ODT input control pin is used to determine when R
on) and off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2].
Timings for ODT are detailed in On-Die Termination (ODT) (page 189).
The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 54 (page 137).
Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as
a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory
modules adopted fly-by topology for the commands, addresses, control signals, and
clocks.
The fly-by topology benefits from a reduced number of stubs and their lengths. Howev-
er, fly-by topology induces flight time skews between the clock and DQS strobe (and
DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining
t
which use fly-by topology-based modules. Write leveling timing and detailed operation
information is provided in Write Leveling (page 125).
POSTED CAS ADDITIVE latency (AL) is supported to make the command and data bus
efficient for sustainable bandwidths in DDR3 SDRAM. MR1[4, 3] define the value of AL,
as shown in Figure 55 (page 140). MR1[4, 3] enable the user to program the DDR3
SDRAM with AL = 0, CL - 1, or CL - 2.
With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank prior to
ACTIVATE to READ or WRITE + AL ≥
DQSS,
t
TT,nom
DSS, and
with R
TT,nom
t
DSH specifications without supporting write leveling in systems
TT
TT(WR)
termination values based on RZQ/n where n can be 2, 4, 6, 8, or
is defined by MR1[9, 6, 2] (see Figure 54 (page 137)). The R
TT,nom
.
139
termination is allowed any time after the DRAM is ini-
TT(EFF)
t
TT(EFF)
RCD (MIN) must be satisfied. Assuming
Micron Technology, Inc. reserves the right to change products or specifications without notice.
, may be different from the R
values and calculations (see On-Die Termi-
2Gb: x4, x8, x16 DDR3 SDRAM
t
RCD (MIN). The only restriction is
Mode Register 1 (MR1)
© 2006 Micron Technology, Inc. All rights reserved.
TT
TT(WR)
is turned on (ODTL
TT
) temporarily re-
targeted due to
t
RCD
TT