MT48H32M16LFBF-75 IT:B Micron Technology Inc, MT48H32M16LFBF-75 IT:B Datasheet - Page 27

• Manufacturer Part Number: MT48H32M16LFBF-75 IT:B
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H32M16LFBF-75 IT:B

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Commands
Table 15: Truth Table – Commands and DQM Operation
Note 1 applies to all parameters and conditions
PDF: 09005aef82ea3742
512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ burst)
WRITE (select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
(enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Notes:
The following table provides a quick reference of available commands, followed by a
written description of each command. Additional Truth Tables (Table 16 (page 33),
Table 17 (page 35), and Table 18 (page 37)) provide current state/next state informa-
tion.
10. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
1. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1
3. A[0:i] provide column address (where i = the most significant column address for a given
4. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when
5. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-
6. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks pre-
7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
9. A[11:0] define the op-code written to the mode register.
determine which bank is made active.
device configuration). A10 HIGH enables the auto precharge feature (nonpersistent),
while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which
bank is being read from or written to.
CKE is LOW.
mand could coincide with data on the bus. However, the DQ column reads a “Don’t
Care” state to illustrate that the BURST TERMINATE command can occur when there is
no data present.
charged and BA0, BA1 are “Don’t Care.”
except for CKE.
delay).
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
27
CS# RAS# CAS# WE# DQM
H
X
X
L
L
L
L
L
L
L
L
H
H
H
H
Micron Technology, Inc. reserves the right to change products or specifications without notice.
X
X
X
L
L
L
L
X
H
H
H
H
X
X
L
L
L
L
H
H
H
H
X
X
X
L
L
L
L
L/H
L/H
X
X
X
X
X
X
X
H
L
© 2007 Micron Technology, Inc. All rights reserved.
Bank/row
Bank/col
Bank/col
Op-code
ADDR
Code
X
X
X
X
X
X
Commands
High-Z
Active
Valid
DQ
X
X
X
X
X
X
X
X
Notes
4, 5
7, 8
10
10
2
3
3
6
9