MT48H32M16LFBF-75 IT:B Micron Technology Inc, MT48H32M16LFBF-75 IT:B Datasheet - Page 6

• Manufacturer Part Number: MT48H32M16LFBF-75 IT:B
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H32M16LFBF-75 IT:B

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
List of Figures
Figure 1: 512Mb Mobile LPSDR Part Numbering .............................................................................................. 2
Figure 2: Functional Block Diagram ................................................................................................................. 9
Figure 3: 54-Ball VFBGA (Top View) ............................................................................................................... 10
Figure 4: 90-Ball VFBGA (Top View) ............................................................................................................... 11
Figure 5: 54-Ball VFBGA (8mm x 9mm) .......................................................................................................... 13
Figure 6: 90-Ball VFBGA (10mm x 13mm) ....................................................................................................... 14
Figure 7: Typical Self Refresh Current vs. Temperature ................................................................................... 19
Figure 8: ACTIVE Command .......................................................................................................................... 28
Figure 9: READ Command ............................................................................................................................. 29
Figure 10: WRITE Command ......................................................................................................................... 30
Figure 11: PRECHARGE Command ................................................................................................................ 31
Figure 12: Initialize and Load Mode Register .................................................................................................. 39
Figure 13: Mode Register Definition ............................................................................................................... 40
Figure 14: CAS Latency .................................................................................................................................. 43
Figure 15: Extended Mode Register Definition ................................................................................................ 44
t
t
t
Figure 16: Example: Meeting
RCD (MIN) When 2 <
RCD (MIN)/
CK < 3 ......................................................... 46
Figure 17: Consecutive READ Bursts .............................................................................................................. 48
Figure 18: Random READ Accesses ................................................................................................................ 49
Figure 19: READ-to-WRITE ............................................................................................................................ 50
Figure 20: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 51
Figure 21: READ-to-PRECHARGE .................................................................................................................. 51
Figure 22: Terminating a READ Burst ............................................................................................................. 52
Figure 23: Alternating Bank Read Accesses ..................................................................................................... 53
Figure 24: READ Continuous Page Burst ........................................................................................................ 54
Figure 25: READ – DQM Operation ................................................................................................................ 55
Figure 26: WRITE Burst ................................................................................................................................. 56
Figure 27: WRITE-to-WRITE .......................................................................................................................... 57
Figure 28: Random WRITE Cycles .................................................................................................................. 58
Figure 29: WRITE-to-READ ............................................................................................................................ 58
Figure 30: WRITE-to-PRECHARGE ................................................................................................................. 59
Figure 31: Terminating a WRITE Burst ........................................................................................................... 60
Figure 32: Alternating Bank Write Accesses .................................................................................................... 61
Figure 33: WRITE – Continuous Page Burst .................................................................................................... 62
Figure 34: WRITE – DQM Operation ............................................................................................................... 63
Figure 35: READ With Auto Precharge Interrupted by a READ ......................................................................... 65
Figure 36: READ With Auto Precharge Interrupted by a WRITE ....................................................................... 66
Figure 37: READ With Auto Precharge ............................................................................................................ 67
Figure 38: READ Without Auto Precharge ....................................................................................................... 68
Figure 39: Single READ With Auto Precharge .................................................................................................. 69
Figure 40: Single READ Without Auto Precharge ............................................................................................. 70
Figure 41: WRITE With Auto Precharge Interrupted by a READ ....................................................................... 71
Figure 42: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 71
Figure 43: WRITE With Auto Precharge .......................................................................................................... 72
Figure 44: WRITE Without Auto Precharge ..................................................................................................... 73
Figure 45: Single WRITE With Auto Precharge ................................................................................................ 74
Figure 46: Single WRITE Without Auto Precharge ........................................................................................... 75
Figure 47: Auto Refresh Mode ........................................................................................................................ 77
Figure 48: Self Refresh Mode ......................................................................................................................... 79
Figure 49: Power-Down Mode ....................................................................................................................... 80
Figure 50: Clock Suspend During WRITE Burst ............................................................................................... 82
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512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN
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