MT48H32M16LFBF-75 IT:B Micron Technology Inc, MT48H32M16LFBF-75 IT:B Datasheet - Page 8

• Manufacturer Part Number: MT48H32M16LFBF-75 IT:B
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H32M16LFBF-75 IT:B

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

General Description
PDF: 09005aef82ea3742
512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN
The 512Mb Mobile LPSDR is a high-speed CMOS, dynamic random-access memory con-
taining 536,870,912-bits. It is internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1K columns
by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 col-
umns by 32 bits. In a reduced page-size option, each of the x32’s 134,217,728-bit banks
is organized as 16,384 rows by 256 columns x32 bits.
Mobile LPSDR offers substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-ad-
dress generation, the ability to interleave between internal banks in order to hide
precharge time, and the capability to randomly change column addresses on each clock
cycle during a burst access.
Note:
1. Throughout the data sheet, various figures and text refer to DQs as DQ. DQ should be
interpreted as any and all DQ collectively, unless specifically stated otherwise. Addition-
ally, the x16 is divided into two bytes: the lower byte and the upper byte. For the lower
byte (DQ[7:0]), DQM refers to LDQM. For the upper byte (DQ[15:8]), DQM refers to
UDQM. The x32 is divided into four bytes. For DQ[7:0], DQM refers to DQM0. For
DQ[15:8], DQM refers to DQM1. For DQ[23:16], DQM refers to DQM2, and for
DQ[31:24], DQM refers to DQM3.
2. Complete functionality is described throughout the document; any page or diagram
may have been simplified to convey a topic and may not be inclusive of all requirements.
3. Any specific requirement takes precedence over a general statement.
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
General Description
© 2007 Micron Technology, Inc. All rights reserved.