EP3C25U256I7 Altera, EP3C25U256I7 Datasheet - Page 19

• Manufacturer Part Number: EP3C25U256I7
• Description: IC CYCLONE III FPGA 25K 256 UBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25U256I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 156
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-UBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 156
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: UFBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 1: Cyclone III Device Data Sheet
Electrical Characteristics
© January 2010 Altera Corporation
Example 1–1
from 25°C at 3.0 V to 85°C at 3.15 V:
Example 1–1.
Because ΔR
Because ΔR
Pin Capacitance
Table 1–9
Table 1–9. Cyclone III Devices Pin Capacitance
C
C
C
C
C
C
C
Notes to
(1) When VREF pin is used as regular input or output, a reduced performance of toggle rate and t
(2) C
Symbol
IOTB
IOLR
LV DSLR
V REFLR
V REFTB
C LKTB
C LKLR
MF
MF
MF = 0.963 × 1.157 = 1.114
R
higher pin capacitance.
VREFTB
final
ΔR
ΔR
(1)
(1)
V
T
Table
= 15.72/100 + 1 = 1.157
= 1 / (3.83/100 + 1) = 0.963
= 50 × 1.114 = 55.71 Ω
V
T
= (3.15 – 3) × 1000 × –0.026 = –3.83
= (85 – 25) × 0.262 = 15.72
for EP3C25 is 30 pF.
lists the pin capacitance for Cyclone III devices.
V
T
Input capacitance on top/bottom I/O pins
Input capacitance on left/right I/O pins
Input capacitance on left/right I/O pins with dedicated
LVDS output
Input capacitance on left/right dual-purpose VREF pin
when used as V
Input capacitance on top/bottom dual-purpose VREF pin
when used as V
Input capacitance on top/bottom dedicated clock input
pins
Input capacitance on left/right dedicated clock input pins
is negative,
is positive,
1–9:
shows you the example to calculate the change of 50 Ω I/O impedance
REF
REF
or user I/O pin
or user I/O pin
Parameter
Cyclone III Device Handbook, Volume 2
Typical –
23
QFP
21
7
8
7
7
6
(2)
Typical –
C O
23
FBGA
is expected due to
21
6
5
7
6
5
(2)
Unit
pF
pF
pF
pF
pF
pF
pF
1–9