EP3C25U256I7 Altera, EP3C25U256I7 Datasheet - Page 72

• Manufacturer Part Number: EP3C25U256I7
• Description: IC CYCLONE III FPGA 25K 256 UBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25U256I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 156
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-UBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 156
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: UFBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

2–28
Table 2–39. Glossary (Part 3 of 5)
Cyclone III Device Handbook, Volume 2
Letter
S
T
Single-ended
Voltage
referenced I/O
Standard
SW (Sampling
Window)
t
TCCS (Channel-
to-channel-skew)
tcin
t
tcout
t
t
t
Timing Unit
Interval (TUI)
t
t
t
tpllcin
tpllcout
C
C O
DUTY
FA LL
H
INJITTER
OUTJITTER_DEDC LK
OUTJITTER_IO
Term
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values.
■
■
After the receiver input crosses the AC value, the receiver changes to the new logic state. The
new logic state is then maintained as long as the input stays beyond the DC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing.
High-speed I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling
window.
High-speed receiver and transmitter input and output clock period.
High-speed I/O Block: The timing difference between the fastest and slowest output edges,
including t
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
High-speed I/O Block: Duty cycle on the high-speed transmitter output clock.
Signal high-to-low transition time (80 to 20%).
Input register hold time.
High-speed I/O block: The timing budget allowed for skew, propagation delays, and the data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Period jitter on the PLL clock input.
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
Delay from the clock pad to the I/O output register.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications.
The DC values indicate the voltage levels at which the final logic state of the receiver is
unambiguously defined.
V
V
OH
OL
C O
variation and clock skew. The clock is included in the TCCS measurement.
V
Definitions
REF
Chapter 2: Cyclone III LS Device Data Sheet
© December 2009 Altera Corporation
V
V
IH(DC)
IL(DC)
V
V
IH ( AC )
IL(AC )
V
CCIO
V
SS
C
/w).
Glossary