EP3C25U256I7 Altera, EP3C25U256I7 Datasheet - Page 28

• Manufacturer Part Number: EP3C25U256I7
• Description: IC CYCLONE III FPGA 25K 256 UBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25U256I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 156
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-UBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 156
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: UFBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

1–18
Periphery Performance
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications
Cyclone III Device Handbook, Volume 2
f
(input clock
frequency)
HSC LK
Symbol
Table 1–25
Table 1–25. Cyclone III Devices JTAG Timing Parameters
High-Speed I/O Specifications
Table 1–26
For definitions of high-speed timing specifications, refer to
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes to
(1) For more information about JTAG waveforms, refer to
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS
JC P
JC H
JC L
JP SU_TDI
JP SU_TM S
JP H
JP CO
JP ZX
JP XZ
JS SU
JS H
JS CO
JS ZX
JS XZ
Symbol
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Modes
Table
×10
×8
×7
×4
×2
×1
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for TDI
JTAG port setup time for TMS
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
lists the JTAG timing parameters and values for Cyclone III devices.
through
1–25:
Table 1–31
Min
10
10
10
10
10
10
Typ
C6
—
—
—
—
—
—
list the high-speed I/O timing for Cyclone III devices.
(2)
Parameter
(2)
Max
180
180
180
180
180
360
(2)
(2)
Min
10
10
10
10
10
10
“JTAG Waveform”
(Note
(2)
(2)
C7, I7
Typ
—
—
—
—
—
—
1),
(Note 1)
155.5
155.5
155.5
155.5
155.5
Max
(2)
311
Chapter 1: Cyclone III Device Data Sheet
in
(Part 1 of 2)
“Glossary” on page
© January 2010 Altera Corporation
“Glossary” on page
Min
10
10
10
10
10
10
C8, A7
Typ
Switching Characteristics
Min
—
—
—
—
—
—
40
20
20
10
—
—
—
10
—
—
—
1
3
5
1–27.
155.5
155.5
155.5
155.5
155.5
Max
311
Max
—
—
—
—
—
—
15
15
15
—
—
25
25
25
1–27.
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns